A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2014, Pages 1588-1591

  Nebashi, Ryusuke ^a   Sakimura, Noboru ^a,b   Honjo, Hiroaki ^a,b   Morioka, Ayuka ^a   Tsuji, Yukihide ^a   Ishihara, Kunihiko ^a   Tokutome, Keiichi ^a   Miura, Sadahiko ^a   Fukami, Shunsuke ^b   Kinoshita, Keizo ^b   Hanyu, Takahiro ^b   Endoh, Tetsuo ^b   Kasai, Naoki ^b   Ohno, Hideo ^b   Sugibayashi, Tadahiko ^a  

^a NEC CORPORATION   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

delay circuit; MRAM; restricted Boltzmann machine; spintronics; time domain signal processing

Indexed keywords

DELAY CIRCUITS; MAGNETIC STORAGE; MAGNETOELECTRONICS; MRAM DEVICES; SIGNAL PROCESSING;

90-NM CMOS; BASIC OPERATION; MRAM; NEUROMORPHIC; POWER EFFICIENT; RESTRICTED BOLTZMANN MACHINE; TEST CHIPS; TIME-DOMAIN SIGNAL;

RANDOM ACCESS STORAGE;

EID: 84907409270     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2014.6865453     Document Type: Conference Paper

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