A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 420-421

  Miyashita, Daisuke ^a   Yamaki, Ryo ^a   Hashiyoshi, Kazunori ^a   Kobayashi, Hiroyuki ^a   Kousai, Shouhei ^a   Oowaki, Yukihito ^a   Unekawa, Yasuo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG COMPUTATION; AREA EFFICIENCY; ARITHMETIC OPERATIONS; DESIGN COMPLEXITY; INTERFACE CIRCUITS; LOGICAL OPERATIONS; LOW DENSITY PARITY CHECK; MIXED-SIGNAL PROCESSING;

ANALOG COMPUTERS;

SIGNAL PROCESSING;

EID: 84876542276     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487796     Document Type: Conference Paper

References (7)

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7. K. Cushon, et al., "A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding," IEEE Trans. Circuits and Systems-II, vol. 57, No. 11, pp. 893-897, 2010