Analyzing reliability of memory sub-systems with double-chipkill detect/correct

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC

Volumn , Issue , 2013, Pages 88-97

  Jian, Xun ^a   Debardeleben, Nathan ^b   Blanchard, Sean ^b   Sridharan, Vilas ^c   Kumar, Rakesh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b LOS ALAMOS NATIONAL LABORATORY   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

chipkill correct; error correcting codes; memory errors; modeling; reliability

Indexed keywords

ANALYTICAL MODELS; ERROR CORRECTION; MODELS; MONTE CARLO METHODS; RELIABILITY;

ANALYTICAL APPROACH; CHIPKILL; CORRECTION OF ERRORS; ERROR CORRECTING CODE; MEMORY ERROR; MEMORY ORGANIZATIONS; MEMORY SUBSYSTEMS; RELIABILITY MODEL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84906764050     PISSN: 15410110     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2013.18     Document Type: Conference Paper

References (18)

1. T. J. Dell, "A White paper on the benefits of chipkill-correct ECC for PC server main memory," IBM Microelectronics Division, Nov, 1997
2. V. Sridharan and D. Liberty, "A study of DRAM failures in the field," in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, ser. SC '12. Los Alamitos, CA, USA: IEEE Computer Society Press, 2012, pp. 76:1-76:11
3. M. Blaum, R. Goodman, and R. McEliece, "The reliability of singleerror protected computer memories," Computers, IEEE Transactions on, vol. 37, no. 1, pp. 114-119, 1988
4. W. F. Mikhail, R. W. Bartoldus, and R. Rutledge, "The reliability of memory with single-error correction," Computers, IEEE Transactions on, vol. C-31, no. 6, pp. 560-564, 1982
5. A. A. Hwang, I. A. Stefanovici, and B. Schroeder, "Cosmic rays don't strike twice: Understanding the nature of DRAM errors and the implications for system design," in Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS XVII. New York, NY, USA: ACM, 2012, pp. 111-122
6. HP, "RAS features of the mission-critical converged infrastruture," June 2010. [Online]. Available: Http://tinyurl.com/d4s6x3k
7. S. S. Mukherjee, J. Emer, T. Fossum, and S. K. Reinhardt, "Cache scrubbing in microprocessors: Myth or necessity?" in Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), ser. PRDC '04. Washington, DC, USA: IEEE Computer Society, 2004, pp. 37-42
8. A. Saleh, J. Serrano, and J. Patel, "Reliability of scrubbing recoverytechniques for memory systems," Reliability, IEEE Transactions on, vol. 39, no. 1, pp. 114-122, 1990
9. L. Schiano, M. Ottavi, and F. Lombardi, "Markov models of faulttolerant memory systems under SEU," in Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on, 2004, pp. 38-43
10. P. Reviriego, J. A. Maestro, and C. Cervantes, "Reliability analysis of memories suffering multiple bit upsets," Device and Materials Reliability, IEEE Transactions on, vol. 7, no. 4, pp. 592-601, 2007
11. J. A. Maestro and P. Reviriego, "Reliability of single-error correction protected memories," Reliability, IEEE Transactions on, vol. 58, no. 1, pp. 193-201, 2009
12. B. Schroeder, E. Pinheiro, and W.-D. Weber, "DRAM errors in the wild: A large-scale field study," in Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems, ser. SIGMETRICS '09. New York, NY, USA: ACM, 2009, pp. 193-204
13. J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber, "Future scaling of processor-memory interfaces," in Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, ser. SC '09. New York, NY, USA: ACM, 2009, pp. 42:1-42:12
14. J. Bent, S. Faibish, J. Ahrens, G. Grider, J. Patchett, P. Tzelnic, and J. Woodring, "Jitter-free co-processing on a prototype exascale storage stack," in Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on, 2012, pp. 1-5
15. K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. S. Williams, and K. Yelick, "Exascale computing study: Technology challenges in achieving exascale systems," 2008. [Online]. Available: Http://www.cse.nd.edu/ Reports/2008/TR-2008-13.pdf
16. S. Amir, M. Asif, and M. Mustafa, "The pivotal role of tera-scale performance in future networks: Sequoia vs multi-core teraflop chip," in Future Networks, 2010. ICFN '10. Second International Conference on, 2010, pp. 265-268
17. P. Coteus, J. Knickerbocker, C. Lam, and Y. Vlasov, "Technologies for exascale systems," IBM Journal of Research and Development, vol. 55, no. 5, pp. 14:1-14:12, 2011
18. A. White, "Exascale challenges: Applications, technologies, and codesign," 2011. [Online]. Available: Https://asc.llnl.gov/exascale/ exascalewhite. Pdf.