System-level assessment and area evaluation of Spin Wave logic circuits

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014

Volumn , Issue , 2014, Pages 25-30

  Zografos, Odysseas ^a,b   Raghavan, Praveen ^a   Amaru, Luca ^c   Sorée, Bart ^d   Lauwereins, Rudy ^a,b   Radu, Iuliana ^a   Verkest, Diederik ^a   Thean, Aaron ^a  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

^c EPFL   (Switzerland)

^d UNIVERSITY OF ANTWERP   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; NANOTECHNOLOGY; SPIN WAVES;

AREA EVALUATIONS; AREA REDUCTION; CMOS TECHNOLOGY; DESIGN FRAMEWORKS; INFORMATION CARRIERS; LOGIC SYNTHESIS TOOLS; MAJORITY GATES; SYSTEM LEVELS;

LOGIC DESIGN;

EID: 84906762151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2014.6880475     Document Type: Conference Paper

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