BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Amaŕu, Luca ^a   Gaillardon, Pierre Emmanuel ^a   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

Author keywords

BDD; Decomposition; Logic synthesis; Majority logic

Indexed keywords

BDD; BINARY DECISION DIAGRAMS (BDDS); DECOMPOSITION METHODS; GENERAL METHODOLOGIES; INTEGRATED SYNTHESIS; LOGIC SYNTHESIS; LOGIC SYNTHESIS TOOLS; SYNTHESIS TECHNIQUES;

BINARY DECISION DIAGRAMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DECOMPOSITION; MAJORITY LOGIC; TOOLS;

LOGIC CIRCUITS;

EID: 84879863779     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488792     Document Type: Conference Paper

References (22)

1. G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw- Hill, New York, 1994.
2. R.L. Rudell, A. Sangiovanni-Vincentelli, Multiple-valued minimization for PLA optimization, IEEE Trans. CAD, Vol. 6, Iss. 5, pp. 727-750, 1987.
3. R.K. Brayton, et al., MIS: A Multiple-Level Logic Optimization System, IEEE Trans. CAD, vol. 6, pp. 1062-1081, Nov.1987.
4. E. Sentovich, et al., SIS: A System for Sequential Circuit Synthesis, ERL, Dept. EECS, Univ. California, Berkeley, UCB/ERL M92/41, 1992.
5. R.K. Brayton, C. Mc Mullen, The Decomposition and Factorization of boolean expressions, Proc. ISCAS 1982.
6. C.Y. Lee, Representation of Switching Circuits by Binary-Decision Programs, Bell Systems Technical Journal, 1959.
7. S.B. Akers, Binary Decision Diagrams, IEEE Trans. Comp., C-27(6):509- 516, June 1978.
8. R.E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Trans. Comput., C-35: 677-691, 1986.
9. V. Bertacco, M. Damiani, The Disjunctive Decomposition of Logic Functions, Proc. ICCAD, 1997.
10. C. Yang and M. Ciesielski, BDS: A BDD-Based Logic Optimization System, IEEE Trans. CAD, vol. 21, pp. 866-876, July 2002.
11. N. Vemuri, P. Kalla and R. Tessier, BDD-based Logic Synthesis for LUTbased FPGAs, ACM Trans. TODAES, Vol.7, pp. 501-525, Oct. 2002.
12. T. Bengtsson, A. Martinelli, E. Dubrova A BDD-Based Fast Heuristic Algorithm for Disjoint Decomposition, Proc. ASP-DAC 2003.
13. S. Plaza, V. Bertacco, STACCATO: Disjoint Support Decompositions from BDDs through Symbolic Kernels, Proc. ASP-DAC 2005.
14. K. Karplus, Using if-then-else DAGs for multi-level logic minimization, Univ. California, Santa Cruz, UCSC-CRL-88-29, 1988.
15. Y. Tohma, Decompositions of Logical Functions Using Majority Decision Elements, IEEE Trans. Electronic Computers, pp. 698-705, 1964.
16. ABC Logic Synthesis Tool [Online]. Available: http://www.eecs.berkeley. edu/alanmi/abc/.
17. O. Coudert, J.C. Madre, A unified framework for the formal verification of sequential circuits, Proc. ICCAD, 1990.
18. O. Coudert, C. Berthet, J.C. Madre, Verification of sequential machines using boolean functional vectors, Proc. International Workshop on Applied Formal Methods for Correct VLSI Design, 1989.
19. K.S. Brace, R.L. Rudell, R.E. Bryant, Efficient implementation of a BDD package, Proc. DAC, 1990.
20. R.E. Bryant, On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication, IEEE Trans. on Computers, vol. 40, no. 2, p. 205, Feb. 1991.
21. R. Chaudry et al., Area-oriented synthesis for PTL, Proc. ICCD 1998.
22. Predictive Technology Model (PTM), http://ptm.asu.edu/.