Device and architecture outlook for beyond CMOS switches

Proceedings of the IEEE

Volumn 98, Issue 12, 2010, Pages 2169-2184

  Bernstein, Kerry ^a   Cavin, Ralph K ^b   Porod, Wolfgang ^c   Seabaugh, Alan ^c   Welser, Jeff ^b,d  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b SEMICONDUCTOR RESEARCH CORPORATION   (United States)

^c UNIVERSITY OF NOTRE DAME   (United States)

^d IBM ALMADEN RESEARCH CENTER   (United States)

Author keywords

Nanoarchitectures; nanomagnet logic; post complementary metal oxide semiconductor (CMOS); pseudospin; quantum dot cellular automata; quantum dot cellular automata architectures (QCAs); spin; tunnel field effect transistor (TFET); tunneling

Indexed keywords

CELLULAR AUTOMATA; DIELECTRIC DEVICES; ELECTRON TUNNELING; METALLIC COMPOUNDS; METALS; MOS DEVICES; NANOCRYSTALS; NANOMAGNETICS; OXIDE SEMICONDUCTORS; SEMICONDUCTOR QUANTUM DOTS; TRANSISTORS; TUNNEL FIELD EFFECT TRANSISTORS;

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; NANOARCHITECTURES; NANOMAGNET LOGIC; PSEUDOSPIN; QUANTUM DOT CELLULAR AUTOMATA; SPIN;

CMOS INTEGRATED CIRCUITS;

EID: 78649987428     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2010.2066530     Document Type: Conference Paper

References (53)

1. D. Jorgenson, "Moore's law and the emergence of the new economy,[ Semiconductor Industry Association, Washington, DC, 2005 Annu. Rep., 2005.
2. G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, 1965.
3. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design for ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256-268, Oct. 1974.
4. R. K. Cavin and V. V. Zhirnov, "Silicon nanoelectronics and beyond: Reflections from a semiconductor industry-government workshop," J. Nanoparticle Res., vol. 8, pp. 137-147, 2004.
5. R. K. Cavin, V. V. Zhirnov, G. I. Bourianoff, J. A. Hutchby, D. J. C. Herr, H. H. Hosack, W. H. Joyner, and T. A. Wooldridge, "A long-term view of research targets in nanoelectronics," J. Nanoparticle Res., vol. 7, pp. 573-586, 2005.
6. R. K. Cavin, V. V. Zhirnov, D. J. C. Herr, A. Avila, and J. Hutchby, "Research directions and challenges in nanoelectronics," J. Nanoparticle Res., vol. 8, pp. 841-858, 2006.
7. A. Geim and K. S. Novoselov, "The rise of graphene," Nature Mater., vol. 6, pp. 183-191, 2007.
8. M. Y. Han, B. Ozyilmaz, Y. Zhang, and P. Kim, Phys. Rev. Lett., vol. 98, 206805, 2007.
9. H. Min, G. Borghi, M. Polini, and A. H. MacDonald, "Pseudospin magnetism in Graphene," Phys. Rev. B, vol. 77, 041407(R), 2008.
10. H. Min, R. Bistritzer, J.-J. Su, and A. H. MacDonald, "Room temperature superfluidity in graphene bilayers," Phys. Rev. B, vol. 78, 121401, 2008.
11. S. K. Banerjee, L. F. Register, E. Tutuc, D. Reddy, and A. H. MacDonald, "Bilayer pseudoSpin Field-Effect Transistor (BiSFET): A proposed new logic device," IEEE Electron Device Lett., vol. 30, no. 2, pp. 158-200, Feb. 2009.
12. S. Datta and B. Das, "Electronic analog of the electro-optic modulator," Appl. Phys. Lett., vol. 56, no. 7, pp. 665-667, Feb. 1990.
13. H. W. Gschwind, Design of Digital Computers. New York: Springer-Verlag, 1967.
14. R. Cowburn and M. Welland, "Room-temperature magnetic quantum cellular automata," Science, vol. 287, no. 5457, pp. 1466-1468, 2000.
15. G. Csaba, A. Imre, G. H. Bernstein, W. Porod, and V. Metlushko, "Nanocompting by field-coupled nanomagnets," IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 209-213, Dec. 2002.
16. A. Imre, G. Csaba, L. Ji, A. Orlov, G. H. Bernstein, and W. Porod, "Majority logic gate for magnetic quantum-dot cellular automata," Science, vol. 311, pp. 205-208, Jan. 2006.
17. C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein, "Quantum cellular automata," Nanotechnology, vol. 4, pp. 49-57, 1993.
18. G. Csaba, W. Porod, and A. I. Csurgay, "A computing architecture composed of field-coupled single-domain nanomagnets clocked by magnetic fields," Int. J. Circuit Theory Appl., vol. 31, pp. 67-82, 2003.
19. D. B. Carlton, N. C. Emley, E. Tuchfeld, J. Bokor, Simulation studies of nanomagnet-based logic architecture, Nano Lett., 8, 4173-4178, Dec., 2008.
20. M. P. Kostylev, A. A. Serga, T. Schneider, B. Leven, and B. Hillebrands, "Spin-wave logical gates," Appl. Phys. Lett., vol. 87, pp. 153501-1-153501-3, 2005.
21. A. Khitun and K. Wang, "Nano scale computational architectures with spin wave bus," Superlattices Microstruct., vol. 38, pp. 184-200, 2005.
22. S. A. Maier, M. L. Brongersma, P. G. Kik, S. Meltzer, A. A. G. Requicha, B. E. Koel, and H. A. Atwater, "PlasmonicsVA route to nanoscale optical devices," Adv. Mater., vol. 13, p. 1501, 2001.
23. K. Song and P. Mazumder, "Active tera hertz (THz) spoof surface plasmon polariton (SPP) switch comprising the perfect conductor meta-material," in Proc. IEEE Nanotechnol. Conf., Genoa, Italy, Jul. 2009, pp. 98-101.
24. J. Hu, X. Ruan, Y. P. Chen, Thermal conductivity and thermal rectification in graphene nanoribbons: A molecular dynamics study, Nano Lett. 9, 7, 2730-2735, 2009, DOI: 10.1021/nl901231s.
25. V. Saripalli, V. Narayanan, and S. Datta, "Ultra low energy binary decision diagram circuits using few electron transistors," Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol. 20. Berlin, Germany: Springer-Verlag, 2009, pp. 200-209.
26. W. Porod et al., "Nanomagnetic logic," in Proc. 1st Berkeley Symp. Energy-Efficient Syst., "erkeley, CA, Jun. 2009.
27. C. Augustine, A. Raychowdhury, Y. Gao, M. Lundstrom, and K. Roy, BPETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices," in Proc. Int. Soc. Qual. Electron. Design, pp. 80-85.
28. A. Khakifirooz and D. A. Antoniadis, "MOSFET performance scalingVPart I: Historical trends," IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1391-1400, Jun. 2008.
29. K. Galatsis, A. Khitun, R. Ostroumov, K. L. Wang, W. R. Dichtel, E. Plummer, J. F. Stoddart, J. L. Zink, J. Y. Lee, Y.-H. Xie, and K. W. Kim, "Alternate state variables for emerging nanoelectronic devices," IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 66-75, Jan. 2009.
30. A. Khitun, M. Bao, J.-Y. Lee, K. L. Wang, D. W. Lee, S. X. Wang, and I. V. Roshchin, "Inductively coupled circuits with spin wave bus for information processing," J. Nanoelectron. Optoelectron., vol. 3, no. 1, pp. 24-34, 2008.
31. A. Khitun, M. Bao, and K. L. Wang, "Spin wave magnetic nanofabric: A new approach to spin-based logic circuitry," IEEE Trans. Magn., vol. 44, no. 9, pp. 2141-2152, Sep. 2008.
32. A. Khitun, D. E. Nikonov, and K. L. Wang, "Magnetoelectric spin wave amplifier for spin wave logic circuits," J. Appl. Phys., vol. 106, 123909, 2009.
33. S. Wolf, J. Lu, M. Stan, E. Chen, and D. Treger, "The promise of nanomagnetics and spintronics for future logic and universal memory," Proc. IEEE, 2010.
34. M. T. Alam, M. J. Siddiq, G. H. Bernstein, M. Niemier, W. Porod, and X. S. Hu, "On-chip clocking for nanomagnetic logic devices IEEE Trans. Nanotechnol., 2010.
35. Q. Zhang, T. Fang, H. Xing, A. Seabaugh, and D. Jena, BGraphene nanoribbon tunnel transistors," IEEE Electron Device Lett., vol. 29, no. 12, pp. 1344-1346, Dec. 2008.
36. H. Chen, L. F. Register, and S. K. Banerjee, "Resonant injection enhanced field effect transistor for low voltage switching: Concept and quantum transport simulation," in Proc. Int. Conf. Simul. Semicond. Processes Devices, San Diego, CA, Sep. 9-11, 2009, DOI: 10.1109/SISPAD.2009.5290247.
37. J.-J. Su and A. H. MacDonald, "How to make a bilayer exciton condensate flow," Nature Phys., vol. 4, pp. 799-802, Oct. 2008.
38. S. K. Banerjee, L. F. Register, E. Tutuc, D. Reddy, and A. H. MacDonald, "Bilayer pseudospin field-effect transistor (BiSFET): A proposed new logic device," IEEE Electron Device Lett., vol. 30, no. 2, pp. 158-160, Feb. 2009.
39. J. Appenzeller, NRI INDEX Annu. Rev., Sep. 25, 2009.
40. B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, "Proposal for an all-spin logic device with built-in memory," Nature Nanotechnol., vol. 5, pp. 266-270, 2010.
41. S. B. Akers, "Binary decision diagrams," IEEE Trans. Comput., vol. C-27, no. 6, pp. 509-516, Jun. 1978.
42. L. Wang and B. Li, "Thermal logic gates: Computation with phonons," Phys. Rev. Lett., vol. 99, 177208, Oct. 2007.
43. J. Hu, X. Ruan, Y. P. Chen, Thermal conductivity and thermal rectification in graphene nanoribbons: A molecular dynamics study, Nano Lett. 9, 7, 2730-2735, 2009.
44. V. V. Chelanov, V. Fal'ko, and B. Altshuler, The focusing of electron flow and a Veselago lens in graphene p-n junctions," Science, vol. 315, 1252-1255, Mar. 2007
45. 3/Si (001) heterostructures," Appl. Phys. Lett., vol. 91, 172513, 2007.
46. A. De, C. E. Pryor, and M. E. Flatte, BElectric-field control of a hydrogenic donor's spin in a semiconductor," Phys. Rev. Lett., vol. 102, 017603, Jan. 2009.
47. International Technology Roadmap for Semiconductors 2008 update. [Online]. Available: http://www.itrs.net/Links/2008ITRS/Update/2008-Update.pdf.
48. M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-power digital design," in Proc. Symp. Low Power Electr., Oct. 1994, pp. 8-11.
49. M. P. Frank, "The physical limits of computing," Comput. Sci. Eng., vol. 4, no. 3, pp. 16-26, May/Jun. 2002.
50. V. V. Zhirnov and R. K. Cavin, III Scaling beyond CMOS: Turing-Heisenberg rapprochement," in Proc. ESSDERC-ESSCIRC, Athens, Greece Sep. 14-18, 2009, DOI: 10.1109/ESSCIRC.2009.5325930.
51. D. Matzke, "Will physical scalability sabotage performance gains?" IEEE Computer, vol. 30, no. 9, pp. 37-39, Sep. 1997.
52. B. S. Landman and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Comput., vol. C-20, no. 12, pp. 1469-1479, Dec. 1971.
53. I. Sutherland et al., Logical Effort: Design Fast CMOS Circuits, 1st ed. San Mateo, CA: Morgan Kaufmann, Feb. 1999, ISBN: 10:1558605576.