Steep-slope devices: From dark to dim silicon

IEEE Micro

Volumn 33, Issue 5, 2013, Pages 50-59

  Swaminathan, Karthik ^a   Kultursay, Emre ^a   Saripalli, Vinay ^a   Narayanan, Vijaykrishnan ^a   Kandemir, Mahmut T ^a   Datta, Suman ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

CMOS TFET heterogeneous architectures; dark silicon; dim silicon; DVFS; dynamic voltage and frequency scaling; power partitioning; steep slope devices; thread migration

Indexed keywords

DARK SILICONS; DVFS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; HETEROGENEOUS ARCHITECTURES; POWER PARTITIONING; STEEP-SLOPE DEVICES; THREAD MIGRATION;

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY;

SILICON;

EID: 84886543112     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2013.75     Document Type: Article

References (4)

1. M.B. Taylor, "Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse," Proc. 49th Ann. Design Automation Conf. (DAC 12), ACM, 2012, pp. 1131-1136.
2. S. Mookerjea et al., "Experimental Demonstration of 100 nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications," Proc. IEEE Int'l Electron Devices Meeting (IEDM 09), IEEE CS, 2009, doi:10.1109/IEDM.2009. 5424355.
3. K. Swaminathan et al., "Improving Energy Efficiency of Multithreaded Applications Using Heterogeneous CMOS-TFET Multicores," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 11), IEEE CS, 2011, pp. 247-252.
4. E. Kultursay et al., "Performance Enhancement under Power Constraints Using Heterogeneous CMOS-TFET Multicores," Proc. Int'l Conf. Hardware/Software Codesign and System Synthesis ACM, 2012, pp. 245-254.