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Volumn 57, Issue , 2014, Pages 388-389

A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

Author keywords

[No Author keywords available]

Indexed keywords

CONVERSION RATES; DISK DRIVE SYSTEMS; DYNAMIC POWER CONSUMPTION; FOLDING FACTOR; HIGH SAMPLING RATES; LOW RESOLUTION; NUMBER OF ZEROS; TIME-INTERLEAVING;

EID: 84898072144     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757482     Document Type: Conference Paper
Times cited : (66)

References (9)
  • 1
    • 77950252888 scopus 로고    scopus 로고
    • A background self-calibrated 6b 2.7GS/s ADC with cascade-calibrated folding-interpolating architecture
    • Apr.
    • Y. Nakajima, et al., "A Background Self-Calibrated 6b 2.7GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture," IEEE J. Solid-State Circuits, vol. 45, pp. 707-718, Apr. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , pp. 707-718
    • Nakajima, Y.1
  • 2
    • 80052652534 scopus 로고    scopus 로고
    • A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture
    • June.
    • T. Yamase, et al., "A 22-mW 7b 1.3-GS/s Pipeline ADC with 1-bit/stage Folding Converter Architecture," Symp. VLSI Circuits, pp. 124-125, June 2011.
    • (2011) Symp. VLSI Circuits , pp. 124-125
    • Yamase, T.1
  • 3
    • 49549089559 scopus 로고    scopus 로고
    • A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS
    • Feb.
    • B. Verbruggen, et al., "A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 252-253
    • Verbruggen, B.1
  • 4
    • 67649921302 scopus 로고    scopus 로고
    • A low-noise self-calibrating dynamic comparator for high-speed ADCs
    • Nov.
    • M. Miyahara, et al., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs", IEEE A-SSCC, pp. 269-272, Nov. 2008.
    • (2008) IEEE A-SSCC , pp. 269-272
    • Miyahara, M.1
  • 5
    • 34250213328 scopus 로고    scopus 로고
    • A 7bit 800Msps 120mW folding and interpolation ADC using a mixed-averaging scheme
    • June.
    • K. Makigawa, et al., "A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme," Symp. VLSI Circuits, pp. 124-125, June 2006.
    • (2006) Symp. VLSI Circuits , pp. 124-125
    • Makigawa, K.1
  • 6
    • 80052664744 scopus 로고    scopus 로고
    • A-104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor
    • June.
    • D. Miyashita, et al., "A-104dBc/Hz In-Band Phase Noise 3GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Convertor," Symp. VLSI Circuits, pp. 112-113, June 2011.
    • (2011) Symp. VLSI Circuits , pp. 112-113
    • Miyashita, D.1
  • 8
    • 84866599674 scopus 로고    scopus 로고
    • A 6b 3GS/s 11mW fully dynamic ADC in 40nm CMOS with reduced number of comparators
    • June.
    • Y.-S Shu, "A 6b 3GS/s 11mW Fully Dynamic ADC in 40nm CMOS with Reduced Number of comparators," Symp. VLSI Circuits, pp. 26-27, June 2012.
    • (2012) Symp. VLSI Circuits , pp. 26-27
    • Shu, Y.-S.1
  • 9
    • 84883803966 scopus 로고    scopus 로고
    • An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI
    • June.
    • V. H.-C. Chen and L. Pileggi, "An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI," Symp. VLSI Circuits, pp. 264-265, June 2013.
    • (2013) Symp. VLSI Circuits , pp. 264-265
    • Chen, V.H.-C.1    Pileggi, L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.