A -104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 112-113

  Miyashita, Daisuke ^a   Kobayashi, Hiroyuki ^a   Deguchi, Jun ^a   Kousai, Shouhei ^a   Hamada, Mototsugu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

ADPLL; phase interpolator; TDC

Indexed keywords

ACTIVE AREA; ADPLL; ALL-DIGITAL PLL; CMOS PROCESSS; IN-BAND PHASE NOISE; LO GENERATION; PHASE INTERPOLATION; PHASE INTERPOLATOR; TDC; TIME-TO-DIGITAL;

CMOS INTEGRATED CIRCUITS; INTERPOLATION; PHASE NOISE; TRANSMITTERS;

VLSI CIRCUITS;

EID: 80052664744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R. B. Staszewski et al., "All-Digital PLL and Transmitter for Mobile Phones," IEEE J. Solid-State Circuits, pp. 2469-2482, Dec. 2005.
2. Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi, "A 2.1-to-2.8GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC," ISSCC Dig. Tech. Papers, pp. 470-471, Feb. 2010.
3. A. Ravi et al., "A 9.2-12GHz, 90nm digital fractional-N synthesizer with stochastic TDC calibration and -35/-41dBc integrated phase noise in the 5/2.5GHz bands," Dig. Symp. VLSI Circuits, pp. 143-144, Jun. 2010.