A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 124-125

  Yamase, Tomoyuki ^a   Uchida, Hiroaki ^a   Noguchi, Hidemi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CONVERTER ARCHITECTURE; CORE AREA; PIPELINE ADCS;

CMOS INTEGRATED CIRCUITS;

VLSI CIRCUITS;

EID: 80052652534     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Z. Cao, S. Yan, and Y.Li, "A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 um CMOS," IEEE JSSC, vol. 44, no.3, pp.862-873, Mar. 2009.
2. S.-W.M. Chen and R.W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-um CMOS," IEEE JSSC, vol.41, no.12, pp.2669-2680, Dec. 2006. (Pubitemid 44955493)
3. Y. Wang and B. Razavi, "An 8-Bit 150-MHz CMOS A/D Converter," IEEE JSSC, vol.35, no. 3, pp. 308-316, Mar. 2000.