A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 26-27

  Shu, Yun Shiang ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

comparator offset calibration; dynamic ADC; flash ADC; interpolation

Indexed keywords

DYNAMIC COMPARATORS; FLASH-ADC; NYQUIST; OFFSET CALIBRATION;

COMPARATORS (OPTICAL); INTERPOLATION; VLSI CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 84866599674     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243772     Document Type: Conference Paper

References (3)

1. B. Verbruggen, et al., "A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 252-254, Feb., 2008.
2. S. Weaver, B. Hershberg, and U. Moon, "Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells," Symp. on VLSI Circuits Dig. Tech. Papers, pp. 266-267, June, 2011.
3. B. Verbruggen, et al., "A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 296-297, Feb., 2010.