Closed-form expression for capacitance of tapered through-silicon-vias considering MOS effect

Proceedings - 2013 14th International Conference on Electronic Packaging Technology, ICEPT 2013

Volumn , Issue , 2013, Pages 1250-1254

  Wang, Fengjuan ^a   Yang, Yintang ^a   Zhu, Zhangming ^a   Liu, Xiaoxian ^a   Zhang, Yan ^a  

^a XIDIAN UNIVERSITY   (China)

Author keywords

MOS Effect; Parasitic Capacitance; Poisson's Equation; Tapered TSV

Indexed keywords

CAPACITANCE; MEAN SQUARE ERROR;

CLOSED-FORM EXPRESSION; MOS EFFECT; PARASITIC CAPACITANCE; POISSON'S EQUATION; ROOT MEAN SQUARE ERRORS; TAPERED TSV; THROUGH SILICON VIAS; THROUGH-SILICON VIA;

ELECTRONICS PACKAGING;

EID: 84898047968     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEPT.2013.6756684     Document Type: Conference Paper

References (11)

1. J. Rosenfeld and E. G. Friedman. "A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits," IEEE Trans. on VLSI Systems, vol. 19, pp. 1075-1085, 2011.
2. L. B. Qian, Z. M. Zhu and Y. T. Yang, "Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits," Microelectronics Journal, vol. 43 pages 128-133, 2012.
3. L. B. Qian, Z. M. Zhu and Y. T. Yang, "Three-dimensional global interconnect based on a design window," Chin. Phys. B, Vol. 20, 108401, 2011.
4. F. J. Wang, Z. M. Zhu, Y. Y. Yang, and N. Wang, "A Thermal Model for the Top Layer of 3D Integrated Circuits Considering Through Silicon Vias," IEEE International Conference on ASIC (ASICON), Xiamen, China, pp. 618-620. Oct. 2011.
5. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, "Electrical Modeling of Through Silicon and Package Vias," IEEE International Conference on 3D System Integration, San Francisco, CA pp. 1-8. Sept. 2009.
6. G. Katti, M. Stucchi, K. D. Meyer, and W. Dehaene, "Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs," IEEE Trans. on Elec. Dev., vol. 57, pp. 256-262, 2010.
7. C. Xu, H. Li, R. Suaya, and K. Banerjee. 'Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs,' IEEE Trans. on Elec. Dev., vol. 57, pp. 3405-3417, 2010.
8. I. Savidis and E. G. Friedman, "Electrical Modeling and Characterization of 3-D Vias," IEEE International Symposium on Circuits and Systems, Seattle, WA, pp. 784-787, May 2008.
9. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, "Electrical Modeling of Annular and Co-axial TSVs Considering MOS Capacitance Effects," IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, Portland, OR, pp. 117-120, Oct. 2009.
10. Y. Liang and Y. Li, "Closed-Form Expressions for the Resistance and the Inductance of Different Profiles of Through-Silicon Vias," IEEE Trans. on Elec. Dev., vol. 32, pp. 393-395, 2011.
11. Z. Xu, J. Q. Lu, High-speed design and broadband modeling of throughstrata-vias (TSVs) in 3D integration, IEEE Trans. on Comp. Pack. Manu. Tech. vol. 1 pp. 154-162. 2011