Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Microelectronics Journal

Volumn 43, Issue 2, 2012, Pages 128-133

  Qian, Libo ^a   Zhu, Zhangming ^a   Yang, Yintang ^a  

^a XIDIAN UNIVERSITY   (China)

Author keywords

3 D ICs; Interconnect delay; Signal reflection; TSV Insertion

Indexed keywords

3-D ICS; 3D ARCHITECTURES; AVERAGE DELAY; DESIGN AND OPTIMIZATION; FIRST ORDER; INTERCONNECT DELAY; MATERIAL CHARACTERISTICS; PARASITIC PARAMETER; PERFORMANCE OPTIMIZATIONS; PHYSICAL DIMENSIONS; PROPAGATION DELAYS; SIGNAL INTEGRITY; SIGNAL REFLECTION; THREE DIMENSIONAL INTEGRATED CIRCUITS; THROUGH-SILICON-VIA; TIMING PERFORMANCE; TSV INSERTION;

INTEGRATED CIRCUITS; INTEGRATION; OPTIMIZATION;

THREE DIMENSIONAL;

EID: 84855874190     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2011.11.004     Document Type: Article

References (28)

1. K. Banerjee, and A. Mehrotra A power-optimal repeater insertion methodology for global interconnects in nanometer designs IEEE Trans. Electron Dev. 49 11 2002 2001 2007
2. X. Liu, Y.T. Peng, and M.C. Papaefthymiou Practical repeater insertion for low power: what repeater library do we need IEEE Trans. ICCAD 25 5 2006 917 924
3. Z.M. Zhu, L.B. Qian, and Y.T. Yang A novel interconnect optimal repeater insertion model with target delay constraint in 65 nm CMOS Chin. Phys. B 18 3 2009 1188 1193
4. M.L. Mui, K. Banerjee, and A. Mehrotra A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth and power dissipation IEEE Trans. Electron Dev. 51 2 2004 195 203
5. Z.M. Zhu, D.J. Wan, and Y.T. Yang An optimization model of wire size for multi-objective constraint Acta Phys. Sin. 59 7 2010 4837 4842
6. V.F. Pavlidis, and E.G. Friedman Three-Dimensional Integrated Circuit Design 2009 Morgan Kaufmann San Mateo
7. J.W. Joyner, R. Venkatesan, and P. Zarkesh-Ha Impact of three-dimensional architecture on interconnect in gigascale integration IEEE Trans. VLSI Syst. 9 6 2000 922 928 (Pubitemid 34126223)
8. A. Rahman, and R. Reif System-level performance evaluation of three-dimensional integrated circuits IEEE Trans. VLSI Syst. 8 6 2000 671 678 (Pubitemid 32254796)
9. R.T. Zhang, K. Roy, and C.K. Koh Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits IEEE Trans. Electron Dev. 48 4 2001 638 652 (Pubitemid 32372222)
10. D.H. Kim, S.K. Lim, Through-silicon-via-aware delay and power prediction for buffed interconnects in 3D ICs, in: Proceeding of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2010, pp. 2531.
11. V.F. Pavlidis, E.G. Friedman, Interconnect delay minimization through interlayer via placement, in: Proceeding of the ACM Great Lakes Symposium on VLSI, 2005, pp. 2025. (Pubitemid 41828790)
12. V.F. Pavlidis, E.G. Friedman, Via placement for minimum interconnect delay in three-dimensional circuits, in: Proceeding of the IEEE International Symposium on Circuit and Systems, 2006, pp. 45874590. (Pubitemid 47132577)
13. Z. Xu, X.H. Jiang, and S. Horiguchi Redundant vias insertion for performance enhancement in 3D ICs IEICE Trans. Electron 91 4 2008 571 580
14. I. Savidis, E.G. Friedman, Electrical modeling and characterization of 3-D vias, in: Proceeding of IEEE International Symposium on Circuit and Systems, 2008, pp. 784787.
15. J.H. Wu, Through Substrate Interconnects for 3-D Integration and RF Systems, Ph.D. Dissertation, MIT, Cambridge, MA, October 2006.
16. G. Katti, M. Stucchi, and K.D. Meyer Electrical modeling and characterization of through silicon via for three-dimensional ICs IEEE Trans. Electron Dev. 57 1 2010 256 262
17. I. Savidis, and E.G. Friedman Closed form expressions of 3-D via resistance, inductance, and capacitance IEEE Trans. Electron Dev. 56 9 2009 1873 1881
18. E.B. Rosa The self and mutual inductance of linear conductors Bull. Bur. Stand. 4 2 1908
19. R. Pucel D. Feny, Gallium Arsenide Technology 1985 Sams Indianapolis
20. L. Cadix, C. Bermond, C. Fuchs, and A. Farcy RF characterization and modeling of high density through silicon vias for 3D chip stacking Microelectron. Eng. 87 3 2010 491 495
21. E.C. Oh, Designs and Applications of Three Dimensional Integrated Circuits, Ph. D. Dissertation, North Carolina State University, Raleigh, North Carolina, July, 2010.
22. T.Y. Chiang, Electro thermal Analysis of VLSI Interconnects, Ph.D. Dissertation, Stanford University, Stanford, California, June, 2004.
23. M.F. Ktata, H. Grabinski, G. Gaus, and H. Fischer When are substrate effects important for on-chip interconnect Electr. Perform. Electron. Packing 2003 265 268
24. Y.I. Ismail, and E.G. Friedman Effect of inductance on the propagation delay and repeater insertion in VLSI circuits IEEE Trans. VLSI Syst. 8 2 2000 199 206
25. M. Avriel Nonlinear Programming: Analysis and Methods 2003 Dover New York
26. B. Bogatin Signal Integrity: Simplified 2003 Prentice Hall PTR Kansas
27. K.Y. Lee, T.C. Wang, K.Y. Chao, Post routing redundant via insertion and line extension with via density consideration, in: Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, 2006, pp. 633640.
28. J.T. Yan, Z.W. Chen, B.Y. Chiang, Y.M. Lee, Timing constrained yield driven redundant via insertion, in: Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008, pp. 16881691.