Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches

Chip in Curitiba 2013 - SBCCI 2013: 26th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2013, Pages

  Gomes, Iuri A C ^a   Kastensmidt, Fernanda G L ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Approximated circuit; TMR; Transient Faults

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUITS; SYSTEMS ANALYSIS; TOPOLOGY;

COMPLEX GATES; FAULT COVERAGES; MAJORITY VOTER; PERMUTATION APPROACH; REDUNDANT MODULES; TMR; TRANSIENT FAULTS; TRIPLE MODULAR REDUNDANCY;

COST REDUCTION;

EID: 84897384071     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2013.6644856     Document Type: Conference Paper

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