Single event transients in combinatorial circuits

SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2005, Pages 121-126

  Wirth, Gilson I ^a   Vieira, Michele G ^a   Neto, Egas Henes ^a   Kastensmidt, F G L ^b  

^a UNIVERSIDADE ESTADUAL DO RIO GRANDE DO SUL   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Integrated circuits; Single event transients; Soft errors

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; CRACK PROPAGATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; ERROR ANALYSIS; FUZZY LOGIC; INTEGRATED CIRCUITS; LOGIC DEVICES; LOGIC GATES; MOBILE TELECOMMUNICATION SYSTEMS; MODAL ANALYSIS; NETWORKS (CIRCUITS); PULSE GENERATORS; SENSITIVITY ANALYSIS; SPICE; SULFATE MINERALS; SYSTEMS ANALYSIS; TRANSIENTS; URANIUM POWDER METALLURGY; VLSI CIRCUITS;

ANALYTICAL MODELLING; AUTOMATED ESTIMATION; AUTOMATED EVALUATION; CIRCUIT LOGIC; CIRCUIT SENSITIVITY; CIRCUIT TOPOLOGIES; ELECTRICAL BEHAVIORS; ELECTRICAL SIMULATIONS; FIRST-ORDER MODELS; MASKING PROPERTIES; MEMORY ELEMENTS; MOS CIRCUITS; SINGLE EVENT TRANSIENT (SET); SINGLE EVENT UPSET (SEU); SOFT-ERROR RATE (SER); SYSTEMS DESIGN; TECHNOLOGY SCALING; TIME CONSUMING; TRANSIENT PULSE;

LOGIC CIRCUITS;

EID: 33750402064     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286843     Document Type: Conference Paper

References (16)

1. T Calvin, F Vargas, M Nicolaidis and R Velazco. "A Low-Cost, Highly Reliable SEU-Tolerant SRAM: Prototype and Test Results", IEEE Trans. Nucl. Sci., vol. 42, pp. 1592-1598, 1995.
2. P Hazucha, C Svensson and S Wender, "Cosmic-Ray Soft Error Characterization of a Standard 0.6-μm CMOS Process", IEEE J. of Solid State Cira, Vol. 35, pp. 1422-1429, 2000.
3. J M Palau, M C Calvet, P E Dodd, F W Sexton and P Roche. "Contribution of Device Simulation to SER Understanding", 41st IEEE Int. Reliability Physics Symposium, Dallas, Texas, p. 71-75, 2003.
4. J M Palau, G Hubert, K Coulie, B Sagnes, and M C Calvet. "Device Simulation Study or the SEU Sensitivity of SRAMs to Ion Tracks Generated by Nuclear Reactions", IEEE Trans. Nucl. Sci., vol. 48, pp. 225-231, 2001.
5. K Castellani-Coulié, J M Palau, G Hubert, M C Calvet, P E Dodd and F Sexton. "Various SEU Conditions in SRAM Studied by 3-D Device Simulation", IEEE Trans. Nucl. Sci., vol. 48, pp. 1931-1936, 2001.
6. F L Yang and R A Saleh, "Simulation and Analysis of Transient Faults in Digital Circuits", IEEE Journal of Solid State Circuits, Vol. 27, pp. 258-264, 1992.
7. J. F. Ziegler, "Terrestrial Cosmic Rays", IBM Journal of R&D, Vol. 40, No. 1, pp. 19-40, 1996.
8. D Alexandrescu, L Anghel, M Nicolaidis, "New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs". 7th IEEE Int. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), Vancouver, BC, Canada, p. 99-107, 2002.
9. G. C. Messenger, "Collection of Charge on Junction Nodes from Ion Tracks", IEEE Trans. Nucl. Sci., vol. NS-29, pp. 2024-2031, 1982.
10. G. R. Srinivasan, "Modeling the Cosmic-Ray-Induced Soft-Error Rate in Integrated Circuits: An Overview", IBM Journal of R&D, Vol. 40, No. 1, pp. 77-90, 1996.
11. P E Dodd and L W Massengill, "Basic Mechanism and Modeling of SEU in Digital Microelectronics", IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, 2003.
12. http://www.austriamicrosystems.com
13. http://www-device.eecs.berkeley.edu
14. A Hirata, H Onodera and K Tamara, "Proposal of a timing model for CMOS logic gates driving a CRC load". Proc. of the 1998 IEEE/ACM Int. Conf. on Computer-Aided Design, San Jose, California, pp. 537-544, 1998.
15. Bellido-Diaz, M.J.; Juan-Chico, J.; Acosta, A.J.; Valencia, M.; and Huertas, J.L., "Logical Modeling of Delay Degradation Effect in Static CMOS Gates". IEE Proc-Circuits Devices Syst. Vol. 147, No. 2, p. 107-117, 2000.
16. Shivakumar, P.; Kistler, M.; Keckler, S.W.; Burger, D.; Alvisi, L.;"Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic". In: International Conference on Dependable Systems and Networks 2002. Proceedings. Piscataway : IEEE Computer Society, pp. 389-398, 2002.