Comparative study of various latch-type sense amplifiers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 22, Issue 2, 2014, Pages 425-429

  Na, Taehui ^a   Woo, Seung Han ^a,b   Kim, Jisu ^a   Jeong, Hanwool ^a   Jung, Seong Ook ^a  

^a Yonsei University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Latch type; mismatch; offset voltage; sense amplifier (SA); sensing dead zone

Indexed keywords

EID: 84895063028     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2013.2239320     Document Type: Article

References (17)

1. Y. Tsiatouhas, A. Chrisanthopoulus, G. Kamoulakos, and T. Han-iotakis, "New memory sense amplifier designs in CMOS technology, " in Proc. IEEE Int. Conf. Electron., Circuits Syst., Feb. 2000, pp. 19-22.
2. R. Sarpeshkar, J. L. Wyatt, N. C. Lu, and P. D. Gerber, "Mismatch sensitivity of a simultaneously latched CMOS sense amplifier, " IEEE J. Solid-State Circuits, vol. 26, no. 10, pp. 1413-1422, Oct. 1991. (Pubitemid 21703493)
3. B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier, " IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004.
4. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture, " IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993. (Pubitemid 23686634)
5. A. Do, Z. Kong, and K. Yeo, "Criterion to evaluate input-offset voltage of a latch-type sense amplifier, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 83-92, Jan. 2010.
6. P. A. Stolk, F. P. Widdershoven, and D. B. M. Klassen, "Modeling statistical dopant fluctuations in MOS transistors, " IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1960-1971, Sep. 1998. (Pubitemid 128736658)
7. T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, Y. Lee, Y. Goto, K. Ito, T. Meguro, H. Takahashi, H. Matsuoka, and H. Ohno, "2Mb SPRAM (spin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read, " IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 109-120, Jan. 2008.
8. W. Y. Cho, B.-H. Cho, B.-G. Choi, H.-R. Oh, S.-B. Kang, K.-S. Kim, K.-H. Kim, D.-E. Kim, C.-K. Kwak, H.-G. Byun, Y.-N. Hwang, S.-J. Ahn, G.-T. Jung, H.-S. Jung, and K. Kim, "A 0.18-μm 3.0V 64-Mb nonvolatile phase-transition random access memory (PRAM), " IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 293-300, Jan. 2005.
9. R. Singh and N. Bhat, "An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 6, pp. 652-657, Jun. 2004.
10. A. J. Bhavnagrwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability, " IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001. (Pubitemid 32407171)
11. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors, " IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
12. K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS, " in Proc. IEEE Int. Electron Device Meeting, Dec. 2007, pp. 471-474.
13. D. Reid, C. Millar, G. Roy, S. Roy, and A. Asenov, "Understanding LER-induced statistical variability: A 35, 000 sample 3D simulation study, " in Proc. Eur. Solid State Device Res. Conf., Sep. 2009, pp. 423-426.
14. A. Asenov, S. Kaya, and J. H. Davies, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations, " IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112-119, Jan. 2002. (Pubitemid 34504288)
15. J. Barth, D. Anand, J. Dreibelbis, and E. Nelson, "A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write, " in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Aug. 2002, pp. 156-157.
16. S. Chung, "Method and system for DRAM sensing, " U.S. Patent 7 369 425, May 6, 2008.
17. W. David, "Sense amplifier having reduced Vt mismatch in input matched differential pair, " U.S. Patent 6445 216, Sep. 3, 2002.