A SPICE model of resistive random access memory for large-scale memory array simulation

IEEE Electron Device Letters

Volumn 35, Issue 2, 2014, Pages 211-213

  Li, Haitong ^a   Huang, Peng ^a   Gao, Bin ^a   Chen, Bing ^a   Liu, Xiaoyan ^a   Kang, Jinfeng ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Circuit simulation; memory array; power dissipation; resistive random access memory (RRAM); SPICE model

Indexed keywords

CONDUCTIVE FILAMENTS; HIGH-RESISTANCE STATE; LOW-RESISTANCE STATE; MEMORY ARRAY; RESISTANCE CAPACITANCE; RESISTIVE RANDOM ACCESS MEMORY; RESISTIVE RANDOM ACCESS MEMORY (RRAM); SPICE MODELING;

CAPACITANCE; CIRCUIT SIMULATION; COMPUTER SIMULATION; ENERGY DISSIPATION; SPICE; TRANSIENTS; WIRE;

RANDOM ACCESS STORAGE;

EID: 84893855405     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2293354     Document Type: Article

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