Scaling challenges for the cross-point resistive memory array to Sub-10nm node - An interconnect perspective

2012 4th IEEE International Memory Workshop, IMW 2012

Volumn , Issue , 2012, Pages

  Liang, Jiale ^a   Yeh, Stanley ^a   Wong, S Simon ^a   Wong, H S Philip ^a  

^a Stanford University   (United States)

Author keywords

cross point; energy; interconnect; latency; reliability; resistive switching memory; scaling; write read margin

Indexed keywords

CROSS-POINT; ENERGY; INTERCONNECT; LATENCY; RESISTIVE SWITCHING MEMORIES; SCALING; WRITE/READ MARGIN;

ENERGY DISSIPATION; NANOTECHNOLOGY; RELIABILITY;

WIRE;

EID: 84864147795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2012.6213650     Document Type: Conference Paper

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