Evolution of CMOS Technology at 32 nm and beyond

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 413-416

  Shahidi, Ghavam G ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

32-NM NODE; CHIP POWER; CMOS SCALING; CMOS TECHNOLOGY; KEY FEATURE; PERFORMANCE GAIN; POWER LIMIT; TECHNOLOGY NODES;

CMOS INTEGRATED CIRCUITS;

EID: 84889872550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405764     Document Type: Conference Paper

References (11)

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11. M. Chudzik, et al, "High-Performance High-/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing", VLSI Tech Dig, 2007.