Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2013, Pages 64-69

  Sharad, Mrigank ^a   Venkatesan, Rangharajan ^a   Raghunathan, Anand ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE HIERARCHIES; COMPUTING PLATFORM; DESIGN ABSTRACTIONS; FUNDAMENTAL DESIGN; READ/WRITE PERFORMANCE; SPIN-BASED DEVICES; SYSTEMATIC EVALUATION; TUNNELING OXIDES;

DESIGN; ENERGY UTILIZATION; LOW POWER ELECTRONICS; MRAM DEVICES; STATIC RANDOM ACCESS STORAGE;

ENERGY EFFICIENCY;

EID: 84889610679     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2013.6629268     Document Type: Conference Paper

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