Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 907-912

  Jiang, Lei ^a   Zhao, Bo ^a   Zhang, Youtao ^b   Yang, Jun ^a  

^a PA 15260   (United States)

^b University of Pittsburgh   (United States)

Author keywords

LLC; MLC; STT MRAM

Indexed keywords

EMBEDDED PROCESSORS; EMERGING NON-VOLATILE MEMORY TECHNOLOGY; L2 CACHE; LLC; MAGNETIC RAMS; MLC; MULTILEVEL CELL; NOVEL DESIGN; SOFT-BIT; SPIN TRANSFER TORQUE; STT-MRAM;

CACHE MEMORY; ENERGY UTILIZATION;

COMPUTER AIDED DESIGN;

EID: 84863549893     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228521     Document Type: Conference Paper

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