Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 10, 1996, Pages 1226-1236

  Chang, Shih Chieh ^a   Marek Sadowska, Malgorzata ^a,c   Hwang, Tingling ^b  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; LOGIC CIRCUITS; LOGIC GATES; PERFORMANCE; TABLE LOOKUP;

BINARY DECISION DIAGRAMS; DONT CARES; FIELD PROGRAMMABLE GATE ARRAY; REDUCED ORDERED BINARY DECISION DIAGRAM; TECHNOLOGY MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030260870     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.541442     Document Type: Article

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