Interconnect patterning in a single step with multi-level nanoimprint lithography

2005 Proceedings - 22nd International VLSI Multilevel Interconnection Conference, VMIC 2005

Volumn , Issue , 2005, Pages 497-502

  Stewart, Michael D ^a,c   Wetzel, Jeff ^b   Palmieri, Frank ^a   Hao, Jianjun ^a   Schmid, Gerard M ^c   Jen, Kane ^a   Nishimura, Yukio ^a   Willson, C Grant ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b ATDF Inc   (United States)

^c MOLECULAR IMPRINTS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL DAMASCENE; ELECTRICAL TESTS; IMPRINTED MATERIALS; INTEGRATED CIRCUIT DEVICES; INTERCONNECT LEVELS; MASK FABRICATION; PROCESSING TIME; STEP-AND-FLASH IMPRINT LITHOGRAPHY;

DIELECTRIC MATERIALS; INTEGRATED CIRCUITS; MASKS; PHOTOLITHOGRAPHY;

NANOIMPRINT LITHOGRAPHY;

EID: 84888356564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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