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Volumn 23, Issue 8, 2013, Pages 385-387

A rigorous model for through-silicon vias with ohmic contact in silicon interposer

Author keywords

Crosstalk; metal oxide semiconductor (MOS) capacitance; ohmic contact; signal integrity; through silicon via (TSV)

Indexed keywords

DOPING DENSITIES; FULL-WAVE SIMULATIONS; METAL OXIDE SEMICONDUCTOR; METAL-SILICON INTERFACES; SIGNAL INTEGRITY; SILICON INTERPOSERS; THROUGH SILICON VIAS; THROUGH-SILICON VIA;

EID: 84882336358     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2013.2270459     Document Type: Article
Times cited : (19)

References (16)
  • 1
    • 79960901040 scopus 로고    scopus 로고
    • High-frequency scalable electrical model and analysis of a through silicon via (TSV)
    • Feb
    • J. Kim et al. , "High-frequency scalable electrical model and analysis of a through silicon via (TSV)," IEEE Trans. Comp. Packag. Manufact. Technol. , vol. 1, no. 2, pp. 181-195, Feb. 2011.
    • (2011) IEEE Trans. Comp. Packag. Manufact. Technol. , vol.1 , Issue.2 , pp. 181-195
    • Kim, L.1
  • 3
    • 78651326478 scopus 로고    scopus 로고
    • Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions
    • Apr
    • K. J. Han et al. , "Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions," IEEE Trans. Adv. Packag. , vol. 33, no. 4, pp. 804-817, Apr. 2010.
    • (2010) IEEE Trans. Adv. Packag. , vol.33 , Issue.4 , pp. 804-817
    • Han, K.J.1
  • 4
    • 80054753153 scopus 로고    scopus 로고
    • Coupling analysis of through-silicon via (TSV) arrays in silicon interposers for 3Dsystems
    • B. Xie, K. J. Han, M. Swaminathan, and J. Xie, "Coupling analysis of through-silicon via (TSV) arrays in silicon interposers for 3Dsystems," in Proc. IEEE Int. Symp. Electromagn. Compat. , 2011, pp. 16-21.
    • (2011) Proc. IEEE Int. Symp. Electromagn. Compat. , pp. 16-21
    • Xie, B.1    Han, K.J.2    Swaminathan, M.3    Xie, J.4
  • 5
    • 73349133689 scopus 로고    scopus 로고
    • Electrical modeling and characterization of through silicon via for three-dimensional ICs
    • G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, vol. 57, pp. 256-262, 2010.
    • (2010) IEEE Trans. Electron Devices , vol.57 , pp. 256-262
    • Katti, G.1    Stucchi, M.2    De Meyer, K.3    Dehaene, W.4
  • 6
    • 84859098960 scopus 로고    scopus 로고
    • High-frequency modeling of TSVs for 3-D chip integration and silicon interposers considering skin-effect, dielectric quasi-TEM and slow-wave modes
    • Oct
    • I. Ndip et al. , "High-frequency modeling of TSVs for 3-D chip integration and silicon interposers considering skin-effect, dielectric quasi-TEM and slow-wave modes," IEEE Trans. Comp. Packag. Manufact. Technol. , vol. 1, no. 10, pp. 1627-1641, Oct. 2011.
    • (2011) IEEE Trans. Comp. Packag. Manufact. Technol. , vol.1 , Issue.10 , pp. 1627-1641
    • Ndip, I.1
  • 7
    • 84866878450 scopus 로고    scopus 로고
    • Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design
    • A. E. Engin and N. S. Raghavan, "Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design," in Proc. IEEE Int. 3D Syst. Integr. Conf. , 2012, pp. 1-4.
    • (2012) Proc. IEEE Int. 3D Syst. Integr. Conf. , pp. 1-4
    • Engin, A.E.1    Raghavan, N.S.2
  • 10
    • 84882433287 scopus 로고    scopus 로고
    • Electrical-thermal modeling of throughsilicon-via (TSV) arrays in interposer
    • Sep
    • J. Xie and M. Swaminathan, "Electrical-thermal modeling of throughsilicon-via (TSV) arrays in interposer," Int. J. Numer. Model. , pp. 1-15, Sep. 2012.
    • (2012) Int. J. Numer. Model. , pp. 1-15
    • Xie, J.1    Swaminathan, M.2
  • 11
    • 84866781930 scopus 로고    scopus 로고
    • Fast extraction of high-frequency parallel admittance of Through-Silicon-Vias and their capacitive coupling-noise to active regions
    • C. Xu, R. Suaya, and K. Banerjee, "Fast extraction of high-frequency parallel admittance of Through-Silicon-Vias and their capacitive coupling-noise to active regions," in Int. Microw. Symp. Dig. , 2012, pp. 1-3.
    • (2012) Int. Microw. Symp. Dig. , pp. 1-3
    • Xu, C.1    Suaya, R.2    Banerjee, K.3
  • 12
    • 84857454206 scopus 로고    scopus 로고
    • Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects
    • T. Bandyopadhyay et al. , "Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects," IEEE Trans. Comp. Packag. Manufact. Technol. , vol. 1, pp. 893-903, 2011.
    • (2011) IEEE Trans. Comp. Packag. Manufact. Technol. , vol.1 , pp. 893-903
    • Bandyopadhyay, T.1
  • 16
    • 84941603444 scopus 로고
    • Prediction of crosstalk in ribbon cables: Comparison of model predictions and experimental results
    • Aug
    • C. Paul, "Prediction of crosstalk in ribbon cables: Comparison of model predictions and experimental results," IEEE Trans. Electromag. Compat. , vol. 20, no. 3, pp. 394-406, Aug. 1978.
    • (1978) IEEE Trans. Electromag. Compat. , vol.20 , Issue.3 , pp. 394-406
    • Paul, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.