QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 643-654

  Pokam, Gilles ^a   Danne, Klaus ^a   Pereira, Cristiano ^a   Kassa, Rolf ^a   Kranich, Tim ^a   Hu, Shiliang ^a   Gottschlich, Justin ^a   Honarmand, Nima ^b   Dautenhahn, Nathan ^b   King, Samuel T ^b   Torrellas, Josep ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Deterministic Record and Replay; FPGA Prototype; Hardware Software Interface; Shared Memory Multiprocessors

Indexed keywords

EMULATION PLATFORM; FPGA PROTOTYPES; HARDWARE PROTOTYPE; MULTI-THREADED PROGRAMS; OPERATING SYSTEM SUPPORT; RECORD-AND-REPLAY; SECOND GENERATION; SHARED MEMORY MULTIPROCESSOR;

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; MICROPROCESSOR CHIPS; RAPID PROTOTYPING;

COMPUTER HARDWARE;

EID: 84881150400     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485977     Document Type: Conference Paper

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