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Volumn , Issue , 2008, Pages 265-276

Rerun: Exploiting episodes for lightweight memory race recording

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL WISDOM; HARDWARE SUPPORTS; INTERNATIONAL SYMPOSIUM; MEMORY ACCESSES; MULTI CORES; NON-DETERMINISM; RACE RECORDING; RECORD INFORMATION; UNIPROCESSOR;

EID: 52649164239     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.26     Document Type: Conference Paper
Times cited : (136)

References (42)
  • 12
    • 52649138697 scopus 로고    scopus 로고
    • Intel. Intel 64 Architecture Memory Ordering White Paper
    • 318147-001, Aug
    • Intel. Intel 64 Architecture Memory Ordering White Paper. Technical Report SKU 318147-001, Intel Corp., Aug. 2007. http://developer.intel.com/ products/processor/manuals/318147. pdf.
    • (2007) Technical Report SKU
  • 13
    • 52649115611 scopus 로고    scopus 로고
    • Making Sequential Consistency Practical in Titanium
    • Nov
    • A. Kamil, J. Su, and K. Yelick. Making Sequential Consistency Practical in Titanium. In Proc. of SC2003, pages 15-30, Nov. 2003.
    • (2003) Proc. of SC2003 , pp. 15-30
    • Kamil, A.1    Su, J.2    Yelick, K.3
  • 15
    • 0017996760 scopus 로고
    • Time, Clocks and the Ordering of Events in a Distributed System
    • July
    • L. Lamport. Time, Clocks and the Ordering of Events in a Distributed System. Communications of the ACM, 21(7):558-565, July 1978.
    • (1978) Communications of the ACM , vol.21 , Issue.7 , pp. 558-565
    • Lamport, L.1
  • 17
  • 18
    • 84863078358 scopus 로고    scopus 로고
    • L. Levrouw and K. Audenaert. Minimizing the Log Size for Execution Replay of Shared-Memory Programs. In Lecture Notes In Computer Science; 854, Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pages 76-87, 1994.
    • L. Levrouw and K. Audenaert. Minimizing the Log Size for Execution Replay of Shared-Memory Programs. In Lecture Notes In Computer Science; Vol. 854, Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pages 76-87, 1994.
  • 33
    • 0031366315 scopus 로고    scopus 로고
    • Efficient Hardware Hashing Functions for High Performance Computers
    • M. Ramakrishna, E. Fu, and E. Bahcekapili. Efficient Hardware Hashing Functions for High Performance Computers. IEEE Transactions on Computers, 46(12): 1378-1381, 1997.
    • (1997) IEEE Transactions on Computers , vol.46 , Issue.12 , pp. 1378-1381
    • Ramakrishna, M.1    Fu, E.2    Bahcekapili, E.3
  • 34
    • 0030721203 scopus 로고    scopus 로고
    • Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models
    • June
    • P. Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proc. of the 9th ACM Symp. on Parallel Algorithms and Architectures, pages 199-210, June 1997.
    • (1997) Proc. of the 9th ACM Symp. on Parallel Algorithms and Architectures , pp. 199-210
    • Ranganathan, P.1    Pai, V.S.2    Adve, S.V.3
  • 36
    • 0004328283 scopus 로고
    • D. L. Weaver and T. Germond, editors, PTR Prentice Hall
    • D. L. Weaver and T. Germond, editors. SPARC Architecture Manual (Version 9). PTR Prentice Hall, 1994.
    • (1994) SPARC Architecture Manual (Version 9)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.