LReplay: A pending period based deterministic replay scheme

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 187-197

  Chen, Yunji ^a,b   Hu, Weiwu ^a,b   Chen, Tianshi ^a,c   Wu, Ruiyang ^a,b  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b Loongson Technologies Corporation Limited   (United States)

^c UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

Author keywords

Deterministic replay; DFD; Global clock; Multi core processor; Pending period; Physical time order

Indexed keywords

DESIGN COSTS; GLOBAL CLOCKS; HARDWARE SUPPORTS; HARDWARE-ASSISTED; MULTI-CORE PROCESSOR; ORDER OF MAGNITUDE; PARALLEL PROGRAM; PERFORMANCE LOSS; SEQUENTIAL CONSISTENCY;

COMPUTER DEBUGGING; COMPUTER HARDWARE; DISTRIBUTED COMPUTER SYSTEMS; NANOTECHNOLOGY; PROGRAM DEBUGGING;

COMPUTER ARCHITECTURE;

EID: 77954993218     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815985     Document Type: Conference Paper

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