-
1
-
-
67650418339
-
Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks
-
A. Kerber and E. Cartier, "Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks,", IEEE Trans. Device Mater. Rel., Vol. 9, no. 2, pp. 147-162, 2009.
-
(2009)
IEEE Trans. Device Mater. Rel.
, vol.9
, Issue.2
, pp. 147-162
-
-
Kerber, A.1
Cartier, E.2
-
2
-
-
0041358085
-
T and β mismatch shifts in pMOSFETs
-
T and β Mismatch Shifts in pMOSFETs,", IEEE Trans. Device Mater. Rel, Vol. 2, No. 4, pg. 89-93, 2002.
-
(2002)
IEEE Trans. Device Mater. Rel
, vol.2
, Issue.4
, pp. 89-93
-
-
Rauch III, S.E.1
-
3
-
-
37549047923
-
Review and reexamination of reliability effects related to NBTI-induced statistical variations
-
Stewart E. Rauch III, "Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations,", IEEE Trans. Device Mater. Rel, Vol. 7, No. 4, pg. 524-530, 2007.
-
(2007)
IEEE Trans. Device Mater. Rel
, vol.7
, Issue.4
, pp. 524-530
-
-
Rauch III, S.E.1
-
4
-
-
51549117124
-
NBTI degradation: From transistor to SRAM arrays
-
V. Huard C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, L. Camus, "NBTI degradation: From Transistor to SRAM Arrays," Proc. Int. Rel. Phys. Symp., p. 289-300, 2008.
-
(2008)
Proc. Int. Rel. Phys. Symp.
, pp. 289-300
-
-
Huard, V.1
Parthasarathy, C.2
Guerin, C.3
Valentin, T.4
Pion, E.5
Mammasse, M.6
Planes, N.7
Camus, L.8
-
5
-
-
77957904660
-
Origin of NBTI variability in deeply scaled pFETs
-
B. Kaczer, T. Grasser, Ph. J. Roussel, J. Franco, R. Degraeve, L.-A. Ragnarsson, E. Simoen, G. Groeseneken, H. Reisinger, "Origin of NBTI Variability in Deeply Scaled pFETs,", Proc. Int. Rel. Phys. Symp., pp.2632, 2010.
-
(2010)
Proc. Int. Rel. Phys. Symp.
, pp. 2632
-
-
Kaczer, B.1
Grasser, T.2
Roussel, Ph.J.3
Franco, J.4
Degraeve, R.5
Ragnarsson, L.-A.6
Simoen, E.7
Groeseneken, G.8
Reisinger, H.9
-
6
-
-
0032320827
-
-
IEEE TED
-
A. Asenov, IEEE TED, "Random Dopant Induced Threshold Voltage Lowering and Fluctuations in sub-0.1 μm MOSFET's: A 3-D "Atomistic" Simulation Study,", Vol. 45, no. 12, pp. 2505-2513, 1998.
-
(1998)
Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 μm MOSFET's: A 3-D "Atomistic" Simulation Study
, vol.45
, Issue.12
, pp. 2505-2513
-
-
Asenov, A.1
-
7
-
-
70549113315
-
2 SRAM and ultra low-k back end with eleven levels of copper
-
2 SRAM and Ultra Low-k Back End with Eleven Levels of Copper,", VLSI, pp. 140-141, 2009.
-
(2009)
VLSI
, pp. 140-141
-
-
Greene, B.1
Liang, Q.2
Amarnath, K.3
Wang, Y.4
Schaeffer, J.5
Cai, M.6
Liang, Y.7
Saroop, S.8
Cheng, J.9
Rotondaro, A.10
Han, S.-J.11
Mo, R.12
McStay, K.13
Ku, S.14
Pal, R.15
Kumar, M.16
Dirahoui, B.17
Yang, B.18
Tamweber, F.19
Lee, W.-H.20
Steigerwalt, M.21
Weijtmans, H.22
Holt, J.23
Black, L.24
Samavedam, S.25
Turner, M.26
Ramani, K.27
Lee, D.28
Belyansky, M.29
Chowdhury, M.30
Aimé, D.31
Min, B.32
Van Meer, H.33
Yin, H.34
Chan, K.35
Angyal, M.36
Zaleski, M.37
Ogunsola, O.38
Child, C.39
Zhuang, L.40
Yan, H.41
Permana, D.42
Sleight, J.43
Guo, D.44
Mittl, S.45
Ioannou, D.46
Wu, E.47
Chudzik, M.48
Park, D.-G.49
Brown, D.50
Luning, S.51
Mocuta, D.52
Maciejewski, E.53
Henson, K.54
Leobandung, E.55
more..
-
8
-
-
77952337060
-
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
-
F. Arnaud, A. Thean, M. Eller, M. Lipinski, Y.W. Teh, M. Ostermayr, K. Kang, N.S. Kim, K. Ohuchi, J-P. Han, D.R. Nair, J. Lian, S. Uchimura, S. Kohler, S. Miyaki, P. Ferreira, J-H. Park, M. Hamaguchi, K. Miyashita, R. Augur, Q. Zhang, K. Strahrenberg, S. ElGhouli, J. Bonnouvrier, F. Matsuoka, R. Lindsay, J. Sudijono, F.S. Johnson, J.H. Ku, M. Sekine, A. Steegen, R. Sampson, "Competitive and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications,", IEDM, pp. 651-654, 2009.
-
(2009)
IEDM
, pp. 651-654
-
-
Arnaud, F.1
Thean, A.2
Eller, M.3
Lipinski, M.4
Teh, Y.W.5
Ostermayr, M.6
Kang, K.7
Kim, N.S.8
Ohuchi, K.9
Han, J.-P.10
Nair, D.R.11
Lian, J.12
Uchimura, S.13
Kohler, S.14
Miyaki, S.15
Ferreira, P.16
Park, J.-H.17
Hamaguchi, M.18
Miyashita, K.19
Augur, R.20
Zhang, Q.21
Strahrenberg, K.22
ElGhouli, S.23
Bonnouvrier, J.24
Matsuoka, F.25
Lindsay, R.26
Sudijono, J.27
Johnson, F.S.28
Ku, J.H.29
Sekine, M.30
Steegen, A.31
Sampson, R.32
more..
-
9
-
-
56549113808
-
Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2/TiN gate stacks
-
A. Kerber, K. Maitra, A. Majumdar, M. Hargrove, R. J. Carter, and E. Cartier, "Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2/TiN gate stacks,", IEEE Trans. Electron Devices, Vol. 55, no. 11, pp. 3175-3183, 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.11
, pp. 3175-3183
-
-
Kerber, A.1
Maitra, K.2
Majumdar, A.3
Hargrove, M.4
Carter, R.J.5
Cartier, E.6
-
10
-
-
0037718399
-
2 dual layer gate dielectrics
-
2 dual layer gate dielectrics," IEEE Electron Device Letters, Vol. 24, No. 2, pp. 87-89, 2003.
-
(2003)
IEEE Electron Device Letters
, vol.24
, Issue.2
, pp. 87-89
-
-
Kerber, A.1
Cartier, E.2
Pantisano, L.3
Degraeve, R.4
Kauerauf, T.5
Kim, Y.6
Hou, A.7
Groeseneken, G.8
Maes, H.E.9
Schwalke, U.10
-
11
-
-
84880977127
-
Electrical characterization methods and their application to metal gate / high-k CMOS reliability evaluation
-
A. Kerber, "Electrical Characterization Methods and their Application to Metal Gate / High-k CMOS Reliability Evaluation,", IPRS tutorial, 2011.
-
(2011)
IPRS Tutorial
-
-
Kerber, A.1
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