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Volumn , Issue , 2009, Pages

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

(32)  Arnaud, F a,b   Thean, A a,c   Eller, M a,d   Lipinski, M a,d   The, Y W a,e   Ostermayr, M a,d   Kang, K a,f   Kim, N S a,e   Ohuchi, K a,g   Han, J P a,d   Nair, D R a,c   Lian, J a,d   Uchimura, S a,g   Kohler, S a,b   Miyaki, S a,h   Ferreira, P a,b   Park, J H a,f   Hamaguchi, M a,g   Miyashita, K a,g   Augur, R a,c   more..


Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; ANALOG DEVICES; AREA REDUCTION; CMOS TECHNOLOGY; COST EFFECTIVE; FULLY COMPATIBLE; GATE DENSITY; HIGH DENSITY WIRING; HIGH-DENSITY; LOW POWER APPLICATION; LOW-POWER DESIGN; MANAGEMENT TECHNIQUES; MATCHING FACTOR; METAL-GATE; METALLIZATIONS; STATIC NOISE MARGIN; SYSTEM ON CHIPS; TRANSISTOR DRIVE CURRENTS;

EID: 77952337060     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424255     Document Type: Conference Paper
Times cited : (38)

References (5)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.