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Volumn , Issue , 2009, Pages
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Competitive and cost effective high-k based 28nm CMOS technology for low power applications
a,b a,c a,d a,d a,e a,d a,f a,e a,g a,d a,c a,d a,g a,b a,h a,b a,f a,g a,g a,c more..
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NEC EL
(United States)
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Author keywords
[No Author keywords available]
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Indexed keywords
45NM TECHNOLOGY;
ANALOG DEVICES;
AREA REDUCTION;
CMOS TECHNOLOGY;
COST EFFECTIVE;
FULLY COMPATIBLE;
GATE DENSITY;
HIGH DENSITY WIRING;
HIGH-DENSITY;
LOW POWER APPLICATION;
LOW-POWER DESIGN;
MANAGEMENT TECHNIQUES;
MATCHING FACTOR;
METAL-GATE;
METALLIZATIONS;
STATIC NOISE MARGIN;
SYSTEM ON CHIPS;
TRANSISTOR DRIVE CURRENTS;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
COST EFFECTIVENESS;
ELECTRIC POWER SUPPLIES TO APPARATUS;
ELECTRON DEVICES;
GATES (TRANSISTOR);
MICROPROCESSOR CHIPS;
STATIC RANDOM ACCESS STORAGE;
TECHNOLOGY;
CMOS INTEGRATED CIRCUITS;
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EID: 77952337060
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IEDM.2009.5424255 Document Type: Conference Paper |
Times cited : (38)
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References (5)
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