Investigation of local bending stress effect on complementary metal-oxide-semiconductor characteristics in thinned si chip for chip-to-wafer three-dimensional integration

Japanese Journal of Applied Physics

Volumn 52, Issue 4 PART 2, 2013, Pages

  Kino, Hisashi ^a   Bea, Ji Choel ^a   Murugesan, Mariappan ^a   Lee, Kang Wook ^a   Fukushima, Takafumi ^a   Koyanagi, Mitsumasa ^a   Tanaka, Tetsu ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INVERTERS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; ELECTRICAL CHARACTERISTIC; LOCAL BENDING STRESS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; TEST STRUCTURE; THREE DIMENSIONAL INTEGRATION; THROUGH SILICON VIAS;

DIELECTRIC DEVICES; FABRICATION; MOSFET DEVICES; SILICON; SOLID STATE DEVICES; THREE DIMENSIONAL;

SILICON WAFERS;

EID: 84880785214     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.7567/JJAP.52.04CB11     Document Type: Conference Paper

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