SCOPUS 정보 검색 플랫폼

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 612-618

Modelling stress in silicon with TSVs and its effect on mobility

(4) Selvanayagam, C S a Zhang, Xiaowu a Rajoo, R a Pinjala, D a

a INSTITUTE OF MICROELECTRONICS (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE DEVICES; COEFFICIENTS OF THERMAL EXPANSIONS; ELECTRICAL CONNECTION; ELECTRICAL INTERCONNECTS; ELECTRICAL PERFORMANCE; ELECTRONICS PRODUCTS; FINITE ELEMENT MODELING; INTERCONNECT CHIPS; JOINT RELIABILITY; SILICON SURFACES; SILICON THICKNESS; STACKING LAYERS; TEMPERATURE LOADINGS; THERMAL MISMATCH; THERMAL STRAIN; THROUGH-SILICON-VIA;

CHIP SCALE PACKAGES; ELASTICITY; ELECTRIC CONNECTORS; STRAIN; STRUCTURAL DESIGN; THERMAL EXPANSION; THERMAL STRESS;

SILICON WAFERS;

EID: 77950930289 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/EPTC.2009.5416477 Document Type: Conference Paper

Times cited : (16)

References (7)

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2
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3
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4
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.