Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 169-170

  Tanaka, T ^a   Kino, H ^a   Nakazawa, R ^a   Kiyoyama, K ^b   Ohno, H ^a   Koyanagi, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NAGASAKI INSTITUTE OF APPLIED SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; LOGIC CHIPS; ON CHIPS; RECONFIGURABLE LSI; SPIN TRANSFER TORQUE; STACKED STRUCTURE; ULTRA-FAST; WRITE SPEED;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84866565446     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242515     Document Type: Conference Paper

References (3)

1. M. Sekikawa et al., Tech. Dig. IEDM, 935-937, 2008.
2. T. Endoh et al., Tech. Dig. IEDM, 75-78, 2011.
3. M. Yamanouchi et al., IEICE Technical Report, 135-138, 2007.