Retention reliability enhanced SONOS NVSM with scaled programming voltage

IEEE Aerospace Conference Proceedings

Volumn 5, Issue , 2002, Pages 2383-2390

  Bu, Jiankang ^a   White, Marvin H ^b  

^a MOTOROLA INC   (United States)

^b LEHIGH UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC CHARACTERIZATION; HIGH TEMPERATURE; LONG-TERM RETENTION; MEASUREMENT SYSTEM; NONVOLATILE MEMORY DEVICES; NONVOLATILE SEMICONDUCTOR MEMORY; PROGRAMMING VOLTAGE; RETENTION TIME;

OPTIMIZATION;

NONVOLATILE STORAGE;

EID: 84879332241     PISSN: 1095323X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AERO.2002.1035411     Document Type: Conference Paper

References (40)

1. M. H. White and D. Adams, "Low-Voltage SONOS Nonvolatile Semiconductor Memories (NVSMs)," GO MAC 2000.
2. Y. Kamigaki, S. Minami, T. Hagiwara, K. Furusawa, T. Furuno, K. lichida, M. Terasawa, and K, Yamazaki, "Yield and reliability of MNOS EEPROM products," IEEE J. Solid-State Circuits, vol. 24, pp. 1714-1722, Dec. 1989. (Pubitemid 20642838)
3. J. Chang. "Nonvolatile Semiconductor Memory Devices," Proc. IEEE, 64(7), pp. 1039-1059, July 1976.
4. F, R. Libsch and M. H. White, SONOS NVSM Chpt. 5, Nonvolatile Semiconductor Memoiy Technology, ed. by W. D. Brown and J.E. Brewer, IEEE Press Series on Microelectronic Systems, pp. 309-357 (1997).
5. N. Ajika, M. Ohi, H. Arima, T. Matsukawa, N. Tsubouchi, "A 5 volt only 16M bit FLASH EEPROM cell with a simple stacked gate structure," in IEDM Tech. Dig., pp. 115-118,1990.
6. S. Asia, Proc. IEEE (74), pp. 1623, 1986.
7. P.C.Y. Chen, "Threshold-alterable Si-gate MOS devices," IEEE Trans. Elect. Dev. ED-24, pp. 584, 1977.
8. E. Takeda, "Hot-carrier and wear-out phenomena in submicron VLSI's," Symp. VLSI Tech., pp.2. Dig. Tech. Papers, Kobe, Japan, 1985.
9. S, Minami, K. Ujiie, M, Terasawa, K. Komori, K. Furusawa, Y. Karn igai. "A3 volt 1 Mbit full-featured EEPROM using a highly-reliable MONOS device technology," IEICE Trans. Elect. Vol. E77-C pp. 12601269,1994.
10. I. Fujiwara, "A 0.13 S Xm MONOS single transistor memoiy cell with separated source lines," Proc. EDM, San Francisco, CA 1998.
11. I. Fujiwara, H. Aozasa, A. Nakamura, Y. Hayashi and T. Kobayashi, "MONOS memory cell scalable to 0.1 .Lm and beyond," Proc. 2000 NVSM Workshop, pp. 117, Monterey, CA 2000.
12. D. Mavis et al., "A reconfigurable nonvolatile radiation hardened FPGA for space applications," Proc. 1998, NASA MAPLD Conf.
13. M. H. White and Y. Yang, "A low voltage SONOS nonvolatile semiconductor memory technology," IEEE Trans. Comp., Pkg and Mfg. Tech., vol. 20, pp. 190 1997.
14. H. C. Wann and C. Hu, "High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application," IEEE Elect. Dev. L., vol. 16, pp. 491, 1995.
15. Y. King, T. King and C. Hu, "A long-refresh dynamic/quasi- nonvolatile memory device with 2 nm tunneling oxide," IEEE Elect. Dev. L., vol. 20, no. 8, pp. 409, 1999.
16. S. Minami and Y. Kamigaki, "A novel MONOS nonvolatile memory device ensuring 10-year data retention after 107 erase/write cycles," IEEE Trans. Elect. Dev., vol. 40, pp. 2011, 1993.
17. H. Reisinger, M. Franosch, B. Hasler and T. Bohrn, "A novel SONOS structure for nonvolatile memories with improved data retention," Symp. VLSI Tech. pp. 113. 1997
18. F. R. Libsch, A. Roy, and M. H. White, "A true 5V EEPROM cell for high density NVSM," IEEE Trans. Elect. Dev., vol 34, pp. 2372,1987.
19. M. L. French and M. H. White, "Scaling of multidielectric nonvolatile SONOS Memory Structures'". Solid-State Elect., vol. 37, pp. 1913, 1995.
20. Y. Yang and M. H. White, "Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures", Solid-State Elect., August 2000.
21. A. Roy, F. R. French, and M. H. White, "Investigations on ultrathin silicon nitride and silicon dioxide films in nonvolatile semiconductor memoiy transistors," Proc. Symp: Silicon Nitride and Silicon Dioxide Thin Insulating Films, San Diego, CA, 1986.
22. T. A. Dellin and J. P. McWhorter, "Scaling MONOS nonvolatile memory transistors," Proc. Symp. Silicon Nitride and Silicon Dioxide Thin Insulating Films, San Diego, CA, 1986.
23. D. Williams, D. Adams, R. Bishop, "Radiation hardened 64K/256K EEPROM technology," Proc. Infl Nonvolatile Memory Tech. Conf pp. 67, 1996.
24. V. J. Kapoor, R. S. Bailey, and R. A. Turi, "Chemical composition, charge trapping, and memory properties of oxynitride films for MNOS devices," J. Electrochem. Soc., vol. 137, pp.3589, 1990.
25. Y. Hu and M. H. White, "Charge retention in scaled SONOS nonvolatile semiconductor memory devices-modeling and characterization," Solid State Elect., vol. 36, pp. 1401,1993.
26. S. Minami and Y, Kamigaki, "Tunnel oxide thickness optimization for high-performance MNOS nonvolatile memory devices," IEICE Trans. Electron., vol. E74, pp.875,1991.
27. M. L. French. C. Y. Chen, H. Sathianathan and M. H. White, "Design and scaling of a SONOS Multidielectric device for nonvolatile memory applications," IEEE Trans. Comp. Pack, and Manu. Tech., part A, vol. 17, no. 3, pp. 390-397, 1994.
28. S. Fujita, H. Toyoshima, M. Nishihara and A. Sasaki, "Variation of trap states and dangling bonds in CVD ShN.j layer on Si substrate by NHySiHj ratio," J. Elec. Mat., vol. (11), no.4, pp.795, 1982.
29. Y. Yang, A. Purwar and M. H. White, "Reliability considerations in scaled SONOS nonvolatile memory devices," Solid State Elect., vol. 43, pp. 2025-2032, 1999. (Pubitemid 30529278)
30. A. B. Joshi, G. Q. Lo, D. K. Kwong, "Improved performance and reliability of MOSFETs with thin gate oxides grown at high temperature," 29th Proc. IRPS, pp. 316, 1991.
31. M. H. White, D. Adams and J. Bu, "On the go with SONOS," IEEE Circuits and Dev., vol. 16, no. 4, pp. 22, 2000.
32. H. E. Maes, S. H. Usmani, and G. L. Heyns, "Effects of a high temperature hydrogen anneal on the memory retention of metal-nitride-oxide- silicon transistors at elevated temperatures," J. Appl. Phys., vol. 52, pp. 4348,1981.
33. Y. Yatsuda, S. Minami, R. Kondo, T. Hagiwara, and Y. Itoh, "Effects of high-temperature hydrogen annealing on n-channel Si-gate MNOS devices," in Proc. 11' Conf. Solid State Devices, Tokyo, 1979; Jpn. J. Appl Phys., vol. 19, suppl. 191, pp. 219-224, 1980.
34. E. T. Foley, A. F. Kam, J. W. Lyding, and Ph. Avouris, "Cryogenic UHV-STM study on hydrogen and deuterium desorbtion from Si(100)," Phys. Rev. Lett., vol. 80, pp. 1336-1339, 1998. (Pubitemid 128626673)
35. J. W. Lyding and K. Hess, "Reduction of hot electron degradation in metal oxide semi-conductor transistors by deuterium processing," Appl. Phys. L., vol. 68, pp. 2526,1996.
36. H. C. Mogul, L. Cong, R. M. Wallace, P. J. Chen, T. A. Rost and K. Harvey, "Electrical and physical characterization of deuterium sinter on submicron devices," Appl. Phys. L., vol. 72. pp. 1721, 1998.
37. F. R. Libsch and M. H. White, "Charge transport and storage of low programming voltage SONOS/MONOS memory devices," Solid-State Elect., vol. 33, pp. 105, 1990.
38. S. Minami, Y. Kamigaki, "New scaling guidelines for MNOS nonvolatile memory devices," IEEE Trans. Elect. Dev., vol. 38, pp. 2519, 1991.
39. R. E. Paulsen and M H. White, "Theoty and application of charge pumping for characterization of Si-Si02 interface and near-interface oxide traps," IEEE. Trans. Electron Devices, vol. 41, no. 7, pp. 1213-1216, 1994.
40. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. de Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vo!. ED-31, pp. 42-53, 1984. (Pubitemid 14561846)