Circuit-level timing-error acceptance for design of energy-efficient DCT/IDCT-based systems

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 23, Issue 6, 2013, Pages 961-974

  He, Ku ^a   Gerstlauer, Andreas ^b   Orshansky, Michael ^b  

^a Cirrus Logic   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Error tolerant computing; low energy design

Indexed keywords

DIGITAL SIGNAL-PROCESSING CIRCUITS; ERROR TOLERANT; IMAGE AND VIDEO PROCESSING; INVERSE DISCRETE COSINE TRANSFORMS; LOW-ENERGY DESIGN; PEAK SIGNAL-TO-NOISE RATIO; REDUCTION IN ENERGY CONSUMPTION; VERY LARGE SCALE INTEGRATION DESIGNS;

COSINE TRANSFORMS; DESIGN; ENERGY EFFICIENCY; ERRORS; TIMING CIRCUITS; VIDEO SIGNAL PROCESSING;

QUALITY CONTROL;

EID: 84878803444     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2013.2243658     Document Type: Article

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