Hardware FPGA implementation of a 2-D median filter using a novel rank adjustment technique

IEE Conference Publication

Volumn , Issue 465 I, 1999, Pages 103-106

  Swenson, R L ^a   Dimond, K R ^a  

^a UNIVERSITY OF KENT   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; NONLINEAR FILTERING; REAL TIME SYSTEMS;

MEDIAN FILTER SYSTEMS;

IMAGE PROCESSING;

EID: 0033359195     PISSN: 05379989     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)