Junctionless tunnel field effect transistor

IEEE Electron Device Letters

Volumn 34, Issue 5, 2013, Pages 584-586

  Ghosh, Bahniman ^a   Akram, Mohammad Waseem ^b  

^a The University of Texas at Austin   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

Author keywords

High k dielectric material; junctionless field effect transistor (JLFET); subthreshold slope (SS); tunnel field effect transistor (TFET)

Indexed keywords

DOUBLE-GATE; GATE LENGTH; HIGH-K DIELECTRIC MATERIALS; JUNCTIONLESS; ROOM TEMPERATURE; SUBTHRESHOLD SLOPE; SWITCHING PERFORMANCE; TUNNEL FIELD EFFECT TRANSISTOR;

DIELECTRIC MATERIALS;

FIELD EFFECT TRANSISTORS;

EID: 84876973676     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2253752     Document Type: Article

References (15)

1. S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. Murali, S. Ganguly, and A. Kottantharayil, "Effect of band-to-band tunneling on junctionless transistors," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1023-1029, Apr. 2012.
2. J. E. Lilienfeld, "Method and apparatus for controlling electric current," U.S. Patent 1 745 175, Oct. 22, 1925.
3. J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. Mc Carthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
4. C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless multigate field-effect transistor," Appl. Phys. Lett., vol. 94, no. 5, pp. 053511-1-053511-2, Feb. 2009.
5. J. P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, and P. Razavi, "Junctionless nanowire transistor (JNT): Properties and design guidelines," Solid State Electron, vols. 65-66, pp. 33-37, Nov.-Dec. 2011.
6. M. T. Bjork, J. Knoch, H. Schmid, H. Riel, and W. Riess, "Silicon nanowire tunneling field-effect transistors," Appl. Phys. Lett., vol. 92, no. 19, pp. 193504-1-193504-3, May 2008.
7. K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with High-κ gate dielectric," IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007. (Pubitemid 47061885)
8. Q. Q. Hung, R. Huang, Z. H. Wang, Z. Zhan, and Y. Y. Wang, "Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage," Appl. Phys. Lett., vol. 99, no. 8, pp. 083507-1-083507-3, Aug. 2011.
9. E. H. Toh, G. H. Wang, G. Q. Lo, L. Chan, G. Samudra, and Y. C. Yeo, "Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering," Appl. Phys. Lett., vol. 99, no. 2, pp. 023505-1-023505-3, Jan. 2007.
10. Silvaco, Version 5.15.32.R. (2009) [Online]. Available: http://www.silvaco.com
11. W. Hansch, T. Vogelsang, R. Kirchner, and M. Orlowski, "Carrier transport near the Si/SiO2 interface of a MOSFET," Solid State Electron., vol. 32, no. 10, pp. 839-849, Oct. 1989. (Pubitemid 20612591)
12. A. Schenk, "A model for the field and temperature dependence of SRH lifetimes in silicon," Solid State Electron., vol. 35, no. 11, pp. 1585-1596, Nov. 1992. (Pubitemid 23579779)
13. D. R. Lide, CRC Handbook on Chemistry and Physics, 89th ed. New York, NY, USA: Taylor & Francis, 2008, pp. 12-114.
14. J. Robertson, "High dielectric constant oxides," Eur. Phys. J. Appl. Phys., vol. 28, no. 3, pp. 265-291, Dec. 2004. (Pubitemid 40002196)
15. K. Boucart and A. M. Ionescu, "Length scaling of the double gate tunnel FET with a High-κ gate dielectric," Solid State Electron., vol. 51, nos. 11-12, pp. 1500-1507, Nov.-Dec. 2007. (Pubitemid 350138020)