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Simple but effective heterogeneous main memory with on-chip memory controller support
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Dynamically variable linesize cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs
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K. Inoue, K. Kai, and K. Murakami. Dynamically variable linesize cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs. HPCA '99.
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HPCA '99
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CHOP: Adaptive filter-based DRAM caching for CMP server platforms
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X. Jiang, N. Madan, L. Zhao, M. Upton, R. Iyer, S. Makineni, D. Newell, Y. Solihin, and R. Balasubramonian. CHOP: Adaptive filter-based DRAM caching for CMP server platforms. HPCA '10.
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Run-time adaptive cache hierarchy management via reference analysis
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Architecting phase change memory as a scalable DRAM alternative
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Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
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G. Loh and M. D. Hill. Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO '11.
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Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
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Scalable high performance main memory system using phase-change memory technology
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M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. ISCA '09.
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Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio
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A. Seznec. Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio. ISCA '94.
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CAT - Caching address tags - A technique for reducing area cost of on-chip caches
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