FinPrin: Analysis and optimization of FinFET logic circuits under PVT variations

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2013, Pages 350-355

  Yang, Yang ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ABSOLUTE ERROR; OPERATING TEMPERATURE; PROCESS VARIATION; PVT VARIATIONS; STATIC TIMING ANALYSIS; STATISTICAL STATIC TIMING ANALYSES (SSTA); TECHNOLOGY NODES; TEMPERATURE VARIATION;

CMOS INTEGRATED CIRCUITS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; LOGIC CIRCUITS; OPTIMIZATION;

INTEGRATED CIRCUITS;

EID: 84875606509     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2013.213     Document Type: Conference Paper

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