Statistical analysis of circuit timing using majorization

Communications of the ACM

Volumn 52, Issue 8, 2009, Pages 95-100

  Orshansky, Michael ^a   Wang, Wei Shen ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL TECHNIQUES; CIRCUIT BEHAVIORS; CIRCUIT DELAY DISTRIBUTIONS; CIRCUIT ELEMENTS; CIRCUIT TIMING; ELECTRONIC DESIGN AUTOMATION TOOLS; EXACT DISTRIBUTION; LOWER BOUNDS; MAJORIZATION; NANOSCALE TRANSISTORS; PROCESS VARIABILITY; ROOT MEAN SQUARES; SILICON TRANSISTORS; STATISTICAL ANALYSIS; STATISTICAL FORMULATION; TIMING ANALYSIS; UPPER BOUND;

COMPUTER AIDED DESIGN; CONTROL THEORY; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUITS; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 69149088515     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/1536616.1536641     Document Type: Article

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