Sneak-path testing of memristor-based memories

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2013, Pages 386-391

  Kannan, Sachhidh ^a   Rajendran, Jeyavijayan ^a   Karri, Ramesh ^a   Sinanoglu, Ozgur ^b  

^a POLYTECHNIC UNIVERSITY   (United States)

^b NEW YORK UNIVERSITY ABU DHABI   (United Arab Emirates)

Author keywords

Emerging memory technologies; Fault modeling; Memory testing; Metal oxide memristors

Indexed keywords

DEFECT MECHANISMS; EMERGING MEMORY TECHNOLOGIES; FAULT MODELING; HIGH DEFECT DENSITIES; LOW-POWER OPERATION; MEMORY TESTING; METAL-OXIDE; NANO-SCALE FABRICATION;

EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; MEMORY ARCHITECTURE; METAL TESTING; PASSIVE FILTERS; RESISTORS; TESTING;

MEMRISTORS;

EID: 84875597204     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2013.219     Document Type: Conference Paper

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