DfT schemes for resistive open defects in RRAMs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 799-804

  Haron, Nor Zaidi ^a,b   Hamdioui, Said ^b  

^a UNIVERSITI TEKNIKAL MALAYSIA MELAKA   (Malaysia)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Design for Testability; memory defect; memristor; quality; reliability

Indexed keywords

CIRCUIT SIMULATION; DEFECTS; DESIGN FOR TESTABILITY; IMAGE QUALITY; RELIABILITY; TESTING;

LOWER-POWER CONSUMPTION; MANUFACTURING TESTS; MEMORY DEFECTS; MEMRISTOR; RANDOM ACCESS MEMORY; RESISTIVE RANDOM ACCESS MEMORY (RRAM); RESISTIVE-OPEN DEFECTS; UNIVERSAL MEMORY;

RRAM;

EID: 84862062637     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176603     Document Type: Conference Paper

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