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A study of thermo-mechanical stress and its impact on through-silicon vias
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Ranganathan, N.1
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Thermo-mechanical reliability of 3-D ICs containing through silicon vias
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Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)
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Modeling thermal conductivity and CTE for CNT-CuComposites for 3-D TSV application
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Analysis of CNT based 3D TSV for emerging RF applications
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June
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A. Gupta, B. C. Kim, S. Kannan, S. S. Evana and L. Li, "Analysis of CNT Based 3D TSV for Emerging RF Applications", Electronic Components and technology Conference, June, 2011.
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Analysis of CNT bundle and its comparison with copper interconnect for CMOS and CNFET drivers
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Kureshi, A.K.1
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Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps
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November
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C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps", IEEE,Transactions on Advanced Packaging, vol. 32, no. 4, November, 2009.
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