Junction engineering of 1T-DRAMs

IEEE Electron Device Letters

Volumn 34, Issue 3, 2013, Pages 408-410

  Giusi, Gino ^a   Iannaccone, Giuseppe ^b  

^a UNIVERSITY OF MESSINA   (Italy)

^b UNIVERSITY OF PISA   (Italy)

Author keywords

Band to band tunneling (BTBT); junctionless (JL); one transistor dynamic random access memory (1T DRAM); random dopant fluctuation; trap assisted tunneling (TAT)

Indexed keywords

BAND TO BAND TUNNELING; JUNCTIONLESS; ONE-TRANSISTOR DYNAMIC RANDOM ACCESS MEMORY (1T-DRAM); RANDOM DOPANT FLUCTUATION; TRAP ASSISTED TUNNELING;

ELECTRIC FIELDS; STRONTIUM COMPOUNDS;

MOSFET DEVICES;

EID: 84874647839     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2239253     Document Type: Article

References (13)

1. S. Okhonin, M. Nagoga, E. Carman, R. Beffa, and E. Faraoni, "New generation of Z-RAM," in Proc. IEEE IEDM, 2007, pp. 925-928.
2. C. Kuo, T. J. King, and C. Hu, "A capacitorless double-gate DRAM cell," IEEE Electron Device Lett., vol. 23, no. 6, pp. 345-347, Jun. 2002. (Pubitemid 34731965)
3. G. Giusi, M. A. Alam, F. Crupi, and S. Pierro, "Bipolar mode operation and scalability of double-gate capacitorless 1T-DRAM cells," IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1743-1750, Aug. 2010.
4. M. Aoulaiche, T. Nicoletti, L. Mendes Almeida, E. Simoen, A. Veloso, P. Blomme, G. Groeseneken, and M. Jurczak, "Junction field effect on retention time for one-transistor floating-body RAM," IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2167-2172, 2012.
5. K.-W. Song, H. Jeong, J.-W. Lee, S. I. Hong, N.-K. Tak, Y.-T. Kim, Y. L. Choi, H. S. Joo, S. H. Kim, H. J. Song, Y. C. Oh, W.-S. Kim, Y.-T Lee, K. Oh, and C. Kim, "55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure," in Proc. IEEE IEDM, 2008, pp. 1-4.
6. M. G. Pala, D. Esseni, and F. Conzatti, "Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: A full quantum study," in Proc. IEEE IEDM, 2012.
7. [Online]. Available: http://www.synopsys.com/Tools/TCAD/DeviceSimulation/ Pages/TaurusMedici.aspx
8. G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, "A new recombination model for device simulation including tunneling," IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331-338, Feb. 1992.
9. D. J. Roulston, N. D. Arora, and S. G. Chamberlain, "Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n+p silicon diodes," IEEE Trans. Electron Devices, vol. ED-29, no. 2, pp. 284-291, Feb. 1982.
10. [Online]. Available: http://www.ioffe.ru/SVA/NSM/Semicond
11. A. Schenk, "Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs," Solid State Electron., vol. 54, no. 2, pp. 115-122, Feb. 2010.
12. P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nature Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
13. C. W. Lee, R. Yan, I. Ferain, A. Kranti, N. D. Akhvan, P. Rasavi, R. Yu, and J. P. Colinge, "Nanowire zero-capacitor DRAM transistors with and without junctions," in Proc. 10th IEEE-NANO, 2010, pp. 242-245.