Subthreshold MOS dynamic translinear neural and synaptic conductance

2011 5th International IEEE/EMBS Conference on Neural Engineering, NER 2011

Volumn , Issue , 2011, Pages 68-71

  Yu, Theodore ^a   Joshi, Siddharth ^a   Rangan, Venkat ^a   Cauwenberghs, Gert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CAPACITANCE SCALING; CURRENT SCALING; HUMAN BRAIN; INTEGRATION DENSITY; LOG-DOMAIN; LOW-POWER REALIZATION; NANOSCALE ELECTRONICS; NEURAL PROSTHESIS; NEUROMORPHIC ENGINEERING; PRACTICAL REALIZATIONS; SINGLE TRANSISTORS; SUBTHRESHOLD; SYNAPTIC CONDUCTANCE; SYNAPTIC DYNAMICS; TRANSISTOR-LEVEL SIMULATION; VOLTAGE-SCALING;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

ENERGY EFFICIENCY;

EID: 79960345880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NER.2011.5910490     Document Type: Conference Paper

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