A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

ISOCC 2012 - 2012 International SoC Design Conference

Volumn , Issue , 2012, Pages 104-107

  Rhim, Jinsoo ^a   Choi, Kwang Chun ^a   Choi, Woo Young ^a  

^a Yonsei University   (South Korea)

Author keywords

65 nm CMOS technology; Clock and data recovery; CMOS static circuits; power and area efficienct

Indexed keywords

10 GB/ S; CHIP AREAS; CLOCK AND DATA RECOVERY; CMOS TECHNOLOGY; POWER AND AREA EFFICIENCT; STATIC CIRCUIT; SUPPLY SENSITIVITY;

CMOS INTEGRATED CIRCUITS;

CLOCKS;

EID: 84873945229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISOCC.2012.6407050     Document Type: Conference Paper

References (11)

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