A 5-Gbit/s clock- and data-recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 56, Issue 1, 2009, Pages 6-10

  Seo, Young Suk ^a   Lee, Jang Woo ^a   Kim, Hong Jung ^a   Yoo, Changsik ^a   Lee, Jae Jin ^b   Jeong, Chun Seok ^b  

^a Hanyang University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Clock and data recovery (CDR); CMOS; Subrate linear phase detector (PD)

Indexed keywords

ANALOG INTEGRATED CIRCUITS; BINARY SEQUENCES; BIT ERROR RATE; CLOCKS; CMOS INTEGRATED CIRCUITS; PHASE COMPARATORS; RECOVERY; SIGNAL DETECTION; TIMING CIRCUITS;

CLOCK AND DATA RECOVERY; CMOS TECHNOLOGY; DATA RATES; LINEAR PHASE DETECTORS; PEAK-TO-PEAK JITTER; PHASE DETECTION; PSEUDO-RANDOM BINARY SEQUENCES;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 59649109205     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.2008520     Document Type: Article

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