A wire-speed power™ processor: 2.3GHz 45nm SOI with 16 cores and 64 threads

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 104-105

  Johnson, Charles ^a   Allen, David H ^b   Brown, Jeff ^b   Vanderwiel, Steve ^b   Hoover, Russ ^b   Achilles, Heather ^a   Cher, Chen Yong ^a   May, George A ^b   Franke, Hubertus ^a   Xenedis, Jimi ^a   Basso, Claude ^b  

^a IBM RESEARCH   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED COMPUTING; HYPERVISOR; I/O DEVICE; IN-LINE; INTEGRATED NETWORKS; LOW POWER; NETWORK PROCESSING; NETWORK PROCESSOR; PROGRAMMING MODELS; SERVER PROCESSORS; SINGLE WIRES; SPEED PROCESSORS; STREAMING APPLICATIONS; TOTAL POWER; TYPICAL APPLICATION; VIRTUALIZATIONS;

NANOTECHNOLOGY; WIRE;

SERVERS;

EID: 77952212767     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434075     Document Type: Conference Paper

References (4)

1. S. Balakrishnan, R. Rajwar, M. Upton, K. Lai, "The Impact of Performance Asymmetry in Emerging Multicore Architectures", ISCA '05, pp. 506-517, June 2005.
2. D.M. Tullsen , S.J. Eggers, H.M. Levy, "Simultaneous multithreading: maximizing on-chip parallelism", ISCA ''95, pp. 392-403, June 22, 1995.
3. M. Keating, D. Flynn, R. Aiken, A. Gibbons, K. Shi. "Low Power Methodology Manual." Springer, 2007, p. 21-24.
4. J.Barth et al, "A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 4, Apr. 2009.