A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 1, 2013, Pages 150-158

  Karl, Eric ^a   Wang, Yih ^a   Ng, Yong Gee ^a   Guo, Zheng ^a   Hamzaoglu, Fatih ^a   Meterelliyoz, Mesut ^a   Keane, John ^a   Bhattacharya, Uddalak ^a   Zhang, Kevin ^a   Mistry, Kaizad ^a   Bohr, Mark ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CMOS integrated circuits; semiconductor memory; SRAM

Indexed keywords

ARRAY DENSITIES; ARRAY DESIGN; BITCELL; CMOS TECHNOLOGY; CO-OPTIMIZATION; HIGH-DENSITY APPLICATIONS; LOGIC TECHNOLOGY; LOW SUPPLY VOLTAGES; LOW VOLTAGES; LOW-VOLTAGE; OPERATING MARGINS; SEMICONDUCTOR MEMORY; SRAM DESIGN; TRANSIENT VOLTAGE; TRI-GATE TRANSISTORS; TRIGATE; WORDLINES;

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

POWER QUALITY;

EID: 84872106571     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2213513     Document Type: Article

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