Shared memory protection for spatial separation in multicore architectures

7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

Volumn , Issue , 2012, Pages 299-302

  Hattendorf, Anton ^a   Raabe, Andreas ^a   Knoll, Alois ^b  

^a FORTISS GMBH   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUS COMMUNICATIONS; MULTI-CORE SYSTEMS; MULTICORE ARCHITECTURES; MULTIPLE APPLICATIONS; SAFETY-CRITICAL; SHARED MEMORIES; SHARED MEMORY ARCHITECTURE; SPATIAL SEPARATION; SYSTEM INTEGRATORS;

EMBEDDED SYSTEMS; SEPARATION; SOFTWARE ARCHITECTURE; STORAGE ALLOCATION (COMPUTER);

MEMORY ARCHITECTURE;

EID: 84871540714     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIES.2012.6356601     Document Type: Conference Paper

References (26)

1. IEC 61508 Functional safety of electrical/electronic/programmable electronic safety-related systems, IEC Std.
2. DO-178B Software Considerations in Airborne Systems and Equipment Certification, Radio Technical Commission for Aeronautics Std.
3. ISO 26262 Road vehicles - Functional safety, ISO Std.
4. ARINC 653-2 Avionics Application Software Standard Interface Part 1 - Required Services, Aeronautical Radio, Inc. Std., December 2005.
5. X. Zhou and P. Petrov, "The interval page table: virtual memory support in real-time and memory-constrained embedded systems," in SBCCI '07. New York: ACM, 2007.
6. "SYSGO PikeOS."
7. C. Aussaguès et al., "PharOS, a multicore OS ready for safety-related automotive systems: results and future prospects," in Embedded Real Time Software and Systems 2010, May 2010.
8. "Wind River Hypervisor."
9. "Green Hills INTEGRITY Multivisor."
10. I. Puaut and D. Hardy, Predictable paging in real-time systems: a compiler approach, 2007.
11. "XMOS." [Online]. Available: http://www.xmos.com/
12. R. Kumar et al., "A system for coarse grained memory protection in tiny embedded processors," in DAC '07. New York: ACM, 2007.
13. N. Ho and A.-V. Dinh-Duc, "MemMON: run-time off-chip detection for memory access violation in embedded systems," in SoICT '10. New York: ACM, 2010.
14. M. Shalan and I. Mooney, V. J., "Hardware support for real-time embedded multiprocessor system-on-a-chip memory management," in CODES 2002, 2002.
15. M. Monchiero et al., "Exploration of Distributed Shared Memory Architecturesfor NoC-based Multiprocessors," in SAMOS 2006, 2006.
16. L. Fiorin et al., "Secure memory accesses on networks-on-chip," IEEE Trans. Comput., 2008.
17. ARM, "ARM Security Technology - Building a Secure System using TrustZone Technology," White Paper.
18. B. Lickly et al., "Predictable programming on a precision timed architecture," in CASES '08. New York, NY, USA: ACM, 2008.
19. "Propeller." [Online]. Available: http://www.parallax.com/ propeller/
20. J. Mische et al., "How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT," ARCS 2010, 2010.
21. R. Obermaisser and B. Huber, "The GENESYS Architecture: A Conceptual Model for Component-Based Distributed Real-Time Systems," in SEUS '09. Berlin, Heidelberg: Springer-Verlag, 2009.
22. A. Jantsch, "Models of Computation for Networks on Chip," in ACSD '06. Washington, DC, USA: IEEE Computer Society, 2006.
23. J. W. Lee, M. C. Ng, and K. Asanovic, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks," in ISCA '08. Washington, DC, USA: IEEE Computer Society, 2008.
24. H. Shah, A. Raabe, and A. Knoll, "Bounding wcet of applications using sdram with priority based budget scheduling in mpsocs," in DATE 2012, 2012.
25. H. Cho et al., "Dynamic data scratchpad memory management for a memory subsystem with an MMU," in LCTES '07. New York, NY, USA: ACM, 2007.
26. M. D. Bennett and N. C. Audsley, Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems, Washington, 2001.