Models of computation for networks on chip

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn , Issue , 2006, Pages 165-176

  Jantsch, Axel ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; BANDWIDTH; ELECTRIC NETWORK TOPOLOGY; SEPARATION;

(PL) PROPERTIES; ABSTRACTION LEVELS; BEST-EFFORT (BE) TRAFFIC; COMPONENT DESIGNS; COMPUTATIONAL MODELLING; GUARANTEED BANDWIDTH; INTERNATIONAL CONFERENCES; MODELS OF COMPUTATION (MOC); NETWORK-ON-CHIP (NOC); NETWORKS ON CHIP (NOCS); POWER CHARACTERISTICS; POWER CONSUMPTION (CE); SYSTEM DESIGNS; SYSTEM LEVELS;

SYSTEMS ANALYSIS;

EID: 36349017476     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2006.14     Document Type: Conference Paper

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